NDLI: VLSI implementation of coupled MRF model using pulse-coupled phase oscillators

Content Provider	IET Digital Library
Author	Matsuzaka, Kenji Tanaka, Hideki Ohkubo, Satoru Morie, Takashi
Abstract	Efficient pixel-parallel image processing using a pulse-coupled phase oscillator model and its very large scale integration (VLSI) implementation is proposed. A processing unit that corresponds to a pixel of an image transmits spike pulses to other units, and updates its own analogue state value at timing when spikes come from other units. From a VLSI implementation point of view, this mechanism is suitable for very low-power operation because analogue buffers are unnecessary for data transmission. On the basis of this model, a VLSI image processor chip that performs a coupled Markov random field model for image region segmentation is designed and fabricated. A very low-power VLSI design has been achieved by the combination of an analogue oscillator and digital coupling function generator circuits with time-domain computation. The processing performance of the fabricated oscillator-based image processor chip using a 0.25 μm CMOS process has achieved 43.2 GOPS or 656 GOPS/W. Experiments using the fabricated chip have shown successful image region segmentation in one- and two-dimensional images.
Starting Page	46
Ending Page	48
Page Count	3
ISSN	00135194
Volume Number	51
e-ISSN	1350911X
Issue Number	Issue 1, Jan (2015)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/51/1
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2014.2105
Journal	Electronics Letters
Publisher	The Institution of Engineering and Technology
Publisher Date	2014-12-08
Access Restriction	Open
Rights License	Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0/)
Subject Keyword	1D Image 2D Image Analogue Buffers Analogue Oscillator Analogue State Value CMOS Analogue Integrated Circuit CMOS Integrated Circuit CMOS Process Computer Vision And Image Processing Technique Coupled Markov Random Field Model Coupled MRF Model Data Transmission Digital Coupling Function Generator Circuit Efficient Pixel-parallel Image Processing Fabricated Chip Image Pixel Image Region Segmentation Image Segmentation Integrated Circuit Design Layout Low Power Electronics Low-power VLSI Design Markov Processes Modelling And Testing One-dimensional Image Optical, Image And Video Signal Processing Oscillator Oscillator-based Image Processor Chip Processing Unit PU Pulse-coupled Phase Oscillator Model Semiconductor Integrated Circuit Design Size 0.25 Mum Spike Pulses Time Domain Analysis Time-domain Computation Very Large Scale Integration Implementation Very Low-power Operation VLSI VLSI Image Processor Chip VLSI Implementation
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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