NDLI: A 312 ps response-time LDO with enhanced super source follower in 28 nm CMOS

Content Provider	IET Digital Library
Author	Lu, Yan Li, Cheng Zhu, Yan Huang, Mo U, Seng Pan Martins, Rui P.
Abstract	High quality fully integrated power supplies could notably improve the performances of the noise-sensitive building block in the UWB communication systems. Double buffers are inserted into the cascode flipped-voltage-follower (FVF) topology to enable designing the dominant pole at the output node for better power supply rejection (PSR) and less voltage variation during load transient. An enhanced super source follower (E-SSF) is proposed to further reduce the output impedance of the buffer that drives the power transistor. The FVF-based low dropout regulator (LDO) with E-SSF achieves a worst-case PSR of −18.9 dB across the full spectrum and a transient response time of 312 ps. The proposed LDO is designed in a 28 nm CMOS process and consumes 100 μA quiescent current with 1.0 V input and 0.8 V output voltages. In total, 120 pF on-chip capacitors are used for filtering.
Starting Page	1368
Ending Page	1370
Page Count	3
ISSN	00135194
Volume Number	52
e-ISSN	1350911X
Issue Number	Issue 16, Aug (2016)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/52/16
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2016.1719
Journal	Electronics Letters
Publisher Date	2016-07-14
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Analogue Circuit Design Buffer Circuit Cascode Flipped-voltage-follower Topology Cascode FVF Topology CMOS Analogue Integrated Circuit CMOS Integrated Circuit CMOS Process Dominant Pole Design Double Buffers E-SSF Electric Impedance Enhanced Super Source Follower FVF-based Low Dropout Regulator High Quality Fully Integrated Power Supplies Integrated Circuit Design Integrated Circuit Noise Load Transient Modelling Noise-sensitive Building Block On-chip Capacitor Output Impedance Reduction Performance Evaluation Performance Improvement Power Electronics Power Integrated Circuit Power Supply Power Supply Circuit Power Supply Rejection Power Transistor Response-time LDO Size 28 Nm Supervisory Circuit Testing Transient Response Time Transients UWB Communication System Voltage 1 V Voltage Regulators Voltage Variation Worst case PSR
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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