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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Hyunho Kim Yongdeuk Ye Sanghyun Choi Jun Lim Soongyu Yim Sung Yi |
| Copyright Year | 2008 |
| Description | Author affiliation: Samsung Electro-Mech. Co. Ltd., Suwon (Hyunho Kim; Yongdeuk Ye; Sanghyun Choi; Jun Lim; Soongyu Yim; Sung Yi) |
| Abstract | Test efficiency of packaged electronics strongly depends on test time and test cost because test time increase causes the increase of test cost. In this paper, with RF WLP devices fabricated by wafer level package processes, we have demonstrated RF multi-DUT testing technology with superior measurement stability and enhanced package yield in RF wafer level test. We could know that RF multi-DUT testing technology for RF WLP devices in wafer level testing has test time reduction of 61.9% compared to test time of RF single-DUT testing through analyzing test time. This technology can offer a number of significant advantages such as productivity improvement and superior capabilities for high performance RF wafer level testing. RF multi-DUT testing technology is essential in addressing future needs for testing RF WLP devices on the wafer. |
| Starting Page | 547 |
| Ending Page | 550 |
| File Size | 9339257 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424428137 |
| DOI | 10.1109/ESTC.2008.4684408 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-09-01 |
| Publisher Place | UK |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Software testing System testing Temperature dependence Costs Electronic equipment testing Optimized production technology test time Wafer scale integration Radio frequency Temperature sensors RF multi-DUT testing RF WLP wafer level testing Electronics packaging test efficiency |
| Content Type | Text |
| Resource Type | Article |
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