NDLI: Die matching algorithm for enhancing parametric yield of 3D ICs

Content Provider	IEEE Xplore Digital Library
Author	Sangdo Park Taewhan Kim
Copyright Year	2012
Description	Author affiliation: School of Electrical Engineering and Computer Science, Seoul National University, Korea (Sangdo Park; Taewhan Kim)
Abstract	This paper addresses the problem of selecting (i.e., matching) dies to be bonded together in 3D IC design to improve parametric yield, producing 3D chips that are highly tolerant to the on-package induced timing variation. For two-layered 3D ICs, the corresponding two-dimensional die-to-die matching problem can be formulated into the maximum bipartite matching problem which is solvable optimally in polynomial time. However, for 3D ICs with K(> 2) layers, the corresponding K-dimensional die-to-die matching problem is known intractable. The previous approach applies the optimal two-dimensional matching algorithm repeatedly to find a solution of the K-dimensional die matching problem. The inherent limitation of the previous approach is that each of the optimal two-dimensional matchings applied in the iteration process is completely isolated and localized, resulting in globally unoptimized K-dimensional matching solutions. This work overcomes this limitation. Precisely, we propose a new enhanced two-dimensional die matching formulation based on finding a maximum flow of minimum cost in a network, which can be solved optimally in polynomial time while facilitating finding globally improved K-dimensional matching solutions when it is iteratively applied. From experimental results with benchmark circuits, we confirm that our proposed algorithm is able to find solutions that produce 5%, 8%, and 12% improved parametric yield for 3-layered, 4-layered, and 5-layered 3D ICs compared to the results of previous work, respectively.
Starting Page	143
Ending Page	146
File Size	135323
Page Count	4
File Format	PDF
ISBN	9781467329897
e-ISBN	9781467329903
e-ISBN	9781467329880
DOI	10.1109/ISOCC.2012.6407060
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-11-04
Publisher Place	Korea (South)
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Integrated circuits Stacking Benchmark testing Polynomials Timing Clocks
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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