NDLI: Automatic Register Transfer level CAD tool design for advanced clock gating and low power schemes

Content Provider	IEEE Xplore Digital Library
Author	Yunlong Zhang Qiang Tong Li Li Wei Wang Ken Choi JongEun Jang Hyobin Jung Si-Young Ahn
Copyright Year	2012
Description	Author affiliation: Epic Solution Inc., 1605 Sang-Am Dong, Ma-Po Gu, Seoul, Rep. of Korea (JongEun Jang; Hyobin Jung; Si-Young Ahn) \|\| Electrical and Computer Engineering, Illinois Institute of Technology, 3301 S Dearborn St., Chicago, 60616, USA (Yunlong Zhang; Qiang Tong; Li Li; Wei Wang; Ken Choi)
Abstract	Power reduction is nowadays becoming the first consideration in VLSI design. Low power is one of major concerns in deeply scaled CMOS technologies. There have been many methods in very wide rang to achieve this objective. And the Register-Transfer level (RTL) has become the most effective stage in low power VLSI design, according to the significant power optimization impact and accurate power estimation. In this paper, some respective low power design techniques at RTL are re-investigated at tsmc 45 nanometer CMOS technology. Clock gating (CG) is one of the most widely used and effective technique in RTL low power design. Without the enable signal, bus-specific clock gating (BSC) and threshold-based clock gating (TCG) are considered. Also an improved active-driven optimized bus-specific clock gating (OBSC) is proposed in our laboratory. When the enable signal is taken into account, this paper explains local-explicit clock gating (LECG), enhanced clock gating (ECG), waste-toggle-rate-based (WTR) clock gating and the single comparator-based clock gating (SCCG) techniques. Operand isolation is another useful design technique for reducing the power consumption by blocking some redundant operations. Memory splitting is an effective design solution for low power design as well. These techniques have been experimented by using tsmc 45nm technology library and the proposed low-power RTL techniques are evaluated at gate level with logic synthesis results.
Starting Page	21
Ending Page	24
File Size	168933
Page Count	4
File Format	PDF
ISBN	9781467329897
e-ISBN	9781467329903
e-ISBN	9781467329880
DOI	10.1109/ISOCC.2012.6406915
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-11-04
Publisher Place	Korea (South)
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Memory splitting Power demand Low power design Operand isolation Clock gating Logic gates Very large scale integration Electrocardiography RTL Delay Optimization Clocks
Content Type	Text
Resource Type	Article

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