NDLI: A Yield Model for Integrated Circuits and its Application to Statistical Timing Analysis

Content Provider	IEEE Xplore Digital Library
Author	Najm, F.N. Menezes, N. Ferzli, I.A.
Copyright Year	1982
Abstract	A model for process-induced parameter variations is proposed, combining die-to-die, within-die systematic, and within-die random variations. This model is put to use toward finding suitable timing margins and device file settings, to verify whether a circuit meets a desired timing yield. While this parameter model is cognizant of within-die correlations, it does not require specific variation models, layout information, or prior knowledge of intrachip covariance trends. The approach works with a "generic" critical path, leading to what is referred to as a "process-specific" statistical-timing-analysis technique that depends only on the process technology, transistor parameters, and circuit style. A key feature is that the variation model can be easily built from process data. The derived results are "full-chip," applicable with ease to circuits with millions of components. As such, this provides a way to do a statistical timing analysis without the need for detailed statistical analysis of every path in the design
Sponsorship	IEEE Council on Electronic Design Automation IEEE Circuits and Systems Society
Starting Page	574
Ending Page	591
Page Count	18
File Size	896443
File Format	PDF
ISSN	02780070
Volume Number	26
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-03-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Integrated circuit modeling Integrated circuit yield Application specific integrated circuits Timing Manufacturing processes Integrated circuit technology Circuit testing Statistical analysis Principal component analysis within-die variations Correlations die-to-die variations generic critical path parametric yield principal component analysis statistical timing analysis timing margin virtual corner
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Electrical and Electronic Engineering Software

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