NDLI: Multi-core architecture for video decoding

Content Provider	IEEE Xplore Digital Library
Author	Jae-Jin Lee KyungJin Byun NakWoong Eum
Copyright Year	2012
Description	Author affiliation: Multimedia Processor Research Team, Electronics and Telecommunications Research Institute, Daejeon, Korea (Jae-Jin Lee; KyungJin Byun; NakWoong Eum)
Abstract	Multiple international video standards in the market have been developed successfully for many commercial products. This paper proposes a new multimedia core and multi-core architecture for multi-standard video decoding. The proposed multimedia core is based on the 6-stage pipelined dual issue VLIW+SIMD architecture and efficient instructions for video decoding. SMIC 130nm process is used for implementation of the proposed architecture whose approximate gate count is about 130K and runs at 125MHz. The multi-core architecture consisting of eight multimedia cores is efficient for parallel decoding of various video compression formats including MPEG-2, MPEG-4, AVS and H.264/AVC.
Starting Page	25
Ending Page	28
File Size	214963
Page Count	4
File Format	PDF
ISBN	9781467329897
e-ISBN	9781467329903
e-ISBN	9781467329880
DOI	10.1109/ISOCC.2012.6406916
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-11-04
Publisher Place	Korea (South)
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multicore processing Video Decoding Multi-Core Transform coding Streaming media Parallel processing Decoding Multimedia communication Multimedia Processor
Content Type	Text
Resource Type	Article

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