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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Youngchan Lee Namdo Kim Kim, J.B. Byeong Min |
| Copyright Year | 2012 |
| Description | Author affiliation: Infrastructure Design Center, Samsung Electronics Co. Ltd., Yongin-City, Korea (Youngchan Lee; Namdo Kim; Kim, J.B.; Byeong Min) |
| Abstract | As power consumption becomes one of the most important characteristics, the number of clocks increases to implement low power features efficiently in modern mobile AP designs. In this circumstance, asynchronous design and “Clock Domain Crossing (CDC)” verification are becoming one of the biggest challenges on over 100M gate SOC designs. Tricky setup due to complex clock relations and complex design, long run time, huge number of false-errors and various operation modes are the known problems of top-level CDC verification. Among the difficulties, 70,000 ∼ 100,000 issues after CDC analysis in an over 100M gate SOC overwhelm designers with its huge volume. This paper presents a comprehensive study on “huge number of false-errors after CDC analysis,” and shows the categories of all types of false-errors and causes, like wrong setups, unidentified static signals, broken asynchronous interfaces etc., which are contributing to a huge number of false-errors. Also, knowledge based solutions for known culprits are presented. It is shown that 95% of false-errors could be eliminated efficiently with the proposed knowledge-based solutions through our 3 case-studies. |
| Starting Page | 391 |
| Ending Page | 394 |
| File Size | 229460 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781467329897 |
| e-ISBN | 9781467329903 |
| e-ISBN | 9781467329880 |
| DOI | 10.1109/ISOCC.2012.6407123 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-11-04 |
| Publisher Place | Korea (South) |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Asynchronous CDC Noise Debugging Logic gates Clock Domain Crossing System-on-a-chip Synchronization Noise measurement Clocks SoC Verification |
| Content Type | Text |
| Resource Type | Article |
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