NDLI: Logic architecture for 2-select arbiter using duel pointer

Content Provider	IEEE Xplore Digital Library
Author	Kalpande, M.D. Vyas, V.
Copyright Year	2015
Description	Author affiliation: Dept. of Electron. Eng., Coll. of Eng. Pune, Pune, India (Kalpande, M.D.; Vyas, V.)
Abstract	Arbitration among various clients, requesting multiple resources simultaneously in high throughput system, needs multiple requests selection in single cycle. A new technique for implementation of arbiter, which selects up to two active request is proposed in this paper. 2 selector circuits are designed by modification of existing parallel prefix tree structures for architecture. Design maintains fairness among active requests by updating pointers according to grant selection algorithm presented. Simulation of design and comparison with previously work is done in terms of area and timing results.
Starting Page	1
Ending Page	5
File Size	687159
Page Count	5
File Format	PDF
ISBN	9781479986392
ISSN	21593450
e-ISBN	9781479986415
DOI	10.1109/TENCON.2015.7373089
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-11-01
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Algorithm design and analysis Round robin Mathematical model Timing Electronic mail Throughput Priority encoder Arbiter Parallel Prefix Tree 2 selector Round Robin Method
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Computer Science Applications

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Logic architecture for 2-select arbiter using duel pointer