NDLI: Enhanced symbolic simulation of a round-robin arbiter

Content Provider	IEEE Xplore Digital Library
Author	Yongjian Li Naiju Zeng Hung, W.N.N. Xiaoyu Song
Copyright Year	2011
Description	Author affiliation: State Key Laboratory of Computer Science, Institute of Software, Chinese Academy of Sciences, Beijing, China (Yongjian Li; Naiju Zeng) \|\| Synopsys Inc., Mountain View, California, USA (Hung, W.N.N.) \|\| ECE Department, Portland State University, Oregon, USA (Xiaoyu Song)
Abstract	In this work, we present our results on formally verifying hardware design of round-robin arbiter which is the core component in many real network systems. Our approach is enhanced STE, which explores fully symbolic simulation for not only one round of round-robin arbitration, but also the sequential behaviors of the arbiter. Our experiments demonstrate that the enhanced STE specification for real-world hardware design can be finished automatically in a reasonable time and memory usage.
Starting Page	102
Ending Page	107
File Size	1063664
Page Count	6
File Format	PDF
ISBN	9781457719530
ISSN	10636404
e-ISBN	9781457719547
DOI	10.1109/ICCD.2011.6081383
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-10-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fabrics Vectors Hardware Integrated circuit modeling Logic gates Control systems Asynchronous transfer mode
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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