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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Si Qing Zheng Mei Yang |
| Copyright Year | 1990 |
| Abstract | As a basic building block of a switch scheduler, a fast and fair arbiter is critical to the efficiency of the scheduler, which is the key to the performance of a high-speed switch or router. In this paper, we propose a parallel round-robin arbiter (PRRA) based on a simple binary search algorithm, which is specially designed for hardware implementation. We prove that our PRRA achieves round-robin fairness under all input patterns. We further propose an improved (IPRRA) design that reduces the timing of PRRA significantly. Simulation results with TSMC .18mum standard cell library show that PRRA and IPRRA can meet the timing requirement of a terabit 256 times 256 switch. Both PRRA and IPRRA are much faster and simpler than the programmable priority encoder (PPE), a well-known round-robin arbiter design. We also introduce an additional design which combines PRRA and IPRRA and provides trade-offs in gate delay, wire delay, and circuit area. With the binary tree structure and high performance, our designs are scalable for large N and useful for implementing schedulers for high-speed switches and routers |
| Sponsorship | IEEE Computer Society |
| File Size | 2861641 |
| File Format | |
| ISSN | 10459219 |
| Volume Number | 18 |
| Issue Number | 1 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-01-01 |
| Publisher Place | U.S.A. |
| Access Restriction | One Nation One Subscription (ONOS) |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Round robin Switches Timing Delay Algorithm design and analysis Hardware Libraries Wire Circuits Binary trees switch scheduling. Arbitration circuits and systems matching parallel processing round-robin arbiter |
| Content Type | Text |
| Resource Type | Article |
| Subject | Signal Processing Computational Theory and Mathematics Hardware and Architecture |
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