NDLI: A technology mapper for depth-constrained FPGA logic cells

Content Provider	IEEE Xplore Digital Library
Author	Zhenghong Jiang Zgheib, G. Lin, C.Y. Novo, D. Zhihong Huang Liqun Yang Haigang Yang Ienne, P.
Copyright Year	2015
Description	Author affiliation: Sch. of Comput. & Commun. Sci., Ecole Polytech. Fed. de Lausanne, Lausanne, Switzerland (Zgheib, G.; Novo, D.; Ienne, P.) \|\| Syst. on Programmable Chip Res. Dept., Inst. of Electron., Beijing, China (Zhenghong Jiang; Lin, C.Y.; Zhihong Huang; Liqun Yang; Haigang Yang)
Abstract	In the last decade, progress in logic synthesis has brought about new advantageous circuit representations. These representations, such as And-Inverter Graphs in the ubiquitous open-source synthesizer ABC, have inspired new designs of Field Programmable Gate Arrays (FPGAs), which, instead of using Look-Up Tables (LUTs), mimic the topology of the circuit representation in the basic logic cells. More recent examples are Majority-Inverter Graphs, another uniform representation which has triggered considerable interest in synthesis and which naturally suggests new logic cells. Yet, in this paper we observe how naïvely adapting technology mapping solutions for classic LUT-based FPGAs to these new architectures incurs severe shortcomings. The key issue is that LUTs are inherently input-constrained (the logic function they implement is irrelevant) and have generally a single output; on the other hand, logic cells made of uniform networks of some fundamental logic function (e.g., And-Invert) are constrained in terms of logic depth and multiple outputs are an integral feature. We introduce novel and effective solutions to address these differences; the result is a highly versatile mapper - thus enabling further research in these new architectures - with a significantly better performance than what is described in literature for one such architecture. Specifically, when we compare with the state of the art on one sample architecture, we obtain a significant decrease in area (on average 18% over several benchmarks) while also improving slightly the critical path (a reduction of 3%).
Starting Page	1
Ending Page	8
File Size	467346
Page Count	8
File Format	PDF
ISBN	9780993428005
DOI	10.1109/FPL.2015.7294014
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-09-02
Publisher Place	UK
Access Restriction	Subscribed
Rights Holder	Imperial College
Subject Keyword	Table lookup Delays Field programmable gate arrays Linear programming Libraries Logic gates
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Xmap: a technology mapper for table-lookup field-programmable gate arrays

Technology mapping for field-programmable gate arrays using integer programming

Chortle: a technology mapping program for lookup table-based field programmable gate arrays

Xtmap: generate-and-test mapper for table-lookup gate arrays

Xmap: A technology mapper for table-lookup field-programmable gate arrays

Process variation immunity of alternative 16nm HK/MG-based FPGA logic blocks

Xmap: a technology mapper for table-lookup field-programmable gate arrays (1991).

Technology mapping of lookup table-based FPGAs for performance

A heuristic method for FPGA technology mapping based on the edge visibility

A technology mapper for depth-constrained FPGA logic cells

Similar Documents

Xmap: a technology mapper for table-lookup field-programmable gate arrays

Technology mapping for field-programmable gate arrays using integer programming

Chortle: a technology mapping program for lookup table-based field programmable gate arrays

Xtmap: generate-and-test mapper for table-lookup gate arrays

Xmap: A technology mapper for table-lookup field-programmable gate arrays

Process variation immunity of alternative 16nm HK/MG-based FPGA logic blocks

Xmap: a technology mapper for table-lookup field-programmable gate arrays (1991).

Technology mapping of lookup table-based FPGAs for performance

A heuristic method for FPGA technology mapping based on the edge visibility

A technology mapper for depth-constrained FPGA logic cells