NDLI: Automatic support for multi-module parallelism from computational patterns

Content Provider	IEEE Xplore Digital Library
Author	George, N. HyoukJoong Lee Novo, D. Owaida, M. Andrews, D. Olukotun, K. Ienne, P.
Copyright Year	2015
Description	Author affiliation: Pervasive Parallelism Lab., Stanford Univ., Stanford, CA, USA (HyoukJoong Lee; Olukotun, K.) \|\| Dept. of Comput. Sci. & Comput. Eng., Univ. of Arkansas, Fayetteville, AR, USA (Andrews, D.) \|\| Sch. of Comput. & Commun. Sci., Ecole Polytech. Fed. de Lausanne, Lausanne, Switzerland (George, N.; Novo, D.; Owaida, M.; Ienne, P.)
Abstract	Field Programmable Gate Arrays (FPGAs) can be customized into application-specific architectures to achieve high performance and energy-efficiency. Unfortunately, they are yet to gain significant adoption by application developers due to their low-level programming model. Moreover, to obtain good performance in an FPGA design, one often needs to correctly parallelize computation and balance the computational throughput with the available data access bandwidth. To address the programming model problem, recent efforts have focused on composing applications out of parallel computational patterns, such as map, reduce, zipWith and foreach, and leveraging the properties of these patterns to generate highly parallel hardware modules capable of high performance. In this work, we focus on the problem of further improving the performance and show that we can utilize the knowledge of how data is consumed and produced by these computational patterns in conjunction with the information of the system architecture to automatically parallelize computations across multiple hardware modules. To achieve this, we automatically infer synchronization needs arising due to parallelization and generate a complete system that can obtain high performance for a given application. We evaluate our approach using seven applications from different domains and show that our automatically generated designs achieve performance improvements ranging from 1.8 to 9.4 times.
Starting Page	1
Ending Page	8
File Size	518748
Page Count	8
File Format	PDF
ISBN	9780993428005
DOI	10.1109/FPL.2015.7294011
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-09-02
Publisher Place	UK
Access Restriction	Subscribed
Rights Holder	Imperial College
Subject Keyword	Kernel Hardware Synchronization Parallel processing Field programmable gate arrays Optimization Bandwidth
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Hardware system synthesis from Domain-Specific Languages

Parallel hardware objects for dynamically partial reconfiguration

Dynamic Stencil: Effective exploitation of run-time resources in reconfigurable clusters

Scalable and Modular Algorithms for Floating-Point Matrix Multiplication on Reconfigurable Computing Systems

Heterogeneous parallel facilities

Memory Parallelism Using Custom Array Mapping to Heterogeneous Storage Structures

From software threads to parallel hardware in high-level synthesis for FPGAs

Multi-query Stream Processing on FPGAs

Scalable Multi-cache Simulation Using GPUs

Automatic support for multi-module parallelism from computational patterns

Similar Documents

Hardware system synthesis from Domain-Specific Languages

Parallel hardware objects for dynamically partial reconfiguration

Dynamic Stencil: Effective exploitation of run-time resources in reconfigurable clusters

Scalable and Modular Algorithms for Floating-Point Matrix Multiplication on Reconfigurable Computing Systems

Heterogeneous parallel facilities

Memory Parallelism Using Custom Array Mapping to Heterogeneous Storage Structures

From software threads to parallel hardware in high-level synthesis for FPGAs

Multi-query Stream Processing on FPGAs

Scalable Multi-cache Simulation Using GPUs

Automatic support for multi-module parallelism from computational patterns