NDLI: SPINE: From C loop-nests to highly efficient accelerators using Algorithmic Species

Content Provider	IEEE Xplore Digital Library
Author	Wijtvliet, M. Fernando, S. Corporaal, H.
Copyright Year	2015
Description	Author affiliation: Dept. of Electr. Eng., Eindhoven Univ. of Technol., Eindhoven, Netherlands (Wijtvliet, M.; Fernando, S.; Corporaal, H.)
Abstract	In modern embedded systems, heterogeneous architectures are crucial in achieving desired performance requirements under area and energy constraints. Many of these systems combine a multi-processor system-on-chip and a Field Programmable Gate Array to enable hardware acceleration. Although the introduction of High-Level Synthesis significantly reduced the complexity of utilizing these systems, a programmer is still required to have expert knowledge of both the High-Level Synthesis tool and the target hardware and to perform time consuming manual iterations to achieve efficient implementations. In this paper we present SPINE, a design flow for automatic generation of efficient hardware accelerators based on Algorithmic Species. SPINE allows the designer to focus on the algorithm by automatically applying hardware specific optimizations and parallelization techniques to the design. As a case study, we present a design space exploration of nine different loop-nests used in image processing kernels and show how SPINE rapidly generates multiple area-performance trade-offs. Furthermore, we compare our results the state of the art and show that SPINE is a promising direction for accelerator generation as the average performance and area improvement with SPINE are respectively 107% and 75% over the state of the art.
Starting Page	1
Ending Page	6
File Size	241941
Page Count	6
File Format	PDF
ISBN	9780993428005
DOI	10.1109/FPL.2015.7294015
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-09-02
Publisher Place	UK
Access Restriction	Subscribed
Rights Holder	Imperial College
Subject Keyword	Kernel Skeleton Hardware design languages Hardware Algorithm design and analysis Field programmable gate arrays Manuals
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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