NDLI: Inter-procedural resource sharing in High Level Synthesis through function proxies

Content Provider	IEEE Xplore Digital Library
Author	Minutoli, M. Castellana, V.G. Tumeo, A. Ferrandi, F.
Copyright Year	2015
Description	Author affiliation: Pacific Northwest Nat. Lab., Richland, WA, USA (Minutoli, M.; Castellana, V.G.; Tumeo, A.) \|\| DEIB, Politec. di Milano, Milan, Italy (Ferrandi, F.)
Abstract	Modular design is becoming increasingly important in High Level Synthesis (HLS) flows. Current HLS flows generate hierarchical and modular designs that mimic the structure and call graph of the input specification by translating functions into modules. Function calls are translated by instantiating the callee module in the data-path of its caller, allowing for resource sharing when the same function is called multiple times. However, if two different callers invoke the same function, current HLS flows cannot share the instance of the module between the two callers, even if they invoke the function in a mutually exclusive way. In this paper, we propose a methodology that enables sharing of (sub)modules across modules boundaries. Sharing is obtained through function proxies, which act as forwarders of function calls in the original specification to shared modules without reducing performance. Building on the concept of function proxies, we propose a methodology and the related components to perform HLS of function calls through function pointers, without requiring complete static knowledge of the alias set (point-to set). We show that module sharing through function proxies provides valuable area savings and no significant impacts on the execution delays, and that our synthesis approach for function pointers enables dynamic polymorphism.
Starting Page	1
Ending Page	8
File Size	167942
Page Count	8
File Format	PDF
ISBN	9780993428005
DOI	10.1109/FPL.2015.7293958
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-09-02
Publisher Place	UK
Access Restriction	Subscribed
Rights Holder	Imperial College
Subject Keyword	Registers Resource management Hardware Corporate acquisitions Benchmark testing Table lookup Optimization
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Function Proxies for Improved Resource Sharing in High Level Synthesis

Automated Synthesis of FSMD-Based Accelerators for Hardware Compilation

Exploiting hardware sharing in high-level synthesis for partial scan optimization

Register allocation for high-level synthesis of hardware accelerators targeting FPGAs

Area-efficient pipelining for FPGA-targeted high-level synthesis

A model-based inter-process resource sharing approach for high-level synthesis of dataflow graphs

Selective Resource Sharing with RT-Level Retiming for Clock Enhancement in High-Level Synthesis

Behavioral-level IP integration in high-level synthesis

Improving polyhedral code generation for high-level synthesis

Inter-procedural resource sharing in High Level Synthesis through function proxies

Similar Documents

Function Proxies for Improved Resource Sharing in High Level Synthesis

Automated Synthesis of FSMD-Based Accelerators for Hardware Compilation

Exploiting hardware sharing in high-level synthesis for partial scan optimization

Register allocation for high-level synthesis of hardware accelerators targeting FPGAs

Area-efficient pipelining for FPGA-targeted high-level synthesis

A model-based inter-process resource sharing approach for high-level synthesis of dataflow graphs

Selective Resource Sharing with RT-Level Retiming for Clock Enhancement in High-Level Synthesis

Behavioral-level IP integration in high-level synthesis

Improving polyhedral code generation for high-level synthesis

Inter-procedural resource sharing in High Level Synthesis through function proxies