NDLI: Process variation immunity of alternative 16nm HK/MG-based FPGA logic blocks

Content Provider	IEEE Xplore Digital Library
Author	Alzahrani, A. DeMara, R.F.
Copyright Year	2015
Description	Author affiliation: Dept. of Electr. Eng. & Comput. Sci., Univ. of Central Florida, Orlando, FL, USA (Alzahrani, A.; DeMara, R.F.)
Abstract	Continued miniaturization of semiconductor technology to nanoscale dimensions has elevated reliability challenges of high density Field-Programmable Gate Arrays (FPGA) devices due to increasing impacts of Process Variation (PV). The issue is addressed herein using a systematic bottom-up analysis by determining the relative influence of PV on alternate design realizations of FPGA logic blocks. Results for conventional design structures are obtained through detailed SPICE simulations and related to structural risk features. Namely, Transmission Gate (TG) and Pass Transistor (PT) based MUX architectures for realizing Look-Up-Tables (LUTs) are compared. At threshold voltage variation $σ_{Vth}$ = 14%, PT-based designs that meet the 95% yield objective can exhibit as high delay variation as 23.3%. PV impact can be reduced to 4.9% if TG-based LUT is considered. Finally, the impact of transistor sizing is investigated as a method of mitigating PV susceptibility in FPGA structures.
Starting Page	1
Ending Page	4
File Size	2073151
Page Count	4
File Format	PDF
e-ISBN	9781467365581
DOI	10.1109/MWSCAS.2015.7282172
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-08-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Transistors Table lookup Delays Logic gates Multiplexing Threshold voltage
Content Type	Text
Resource Type	Article

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