NDLI: A scalable FPGA architecture for nonnegative least squares problems

Content Provider	IEEE Xplore Digital Library
Author	Althoff, A. Kastner, R.
Copyright Year	2015
Description	Author affiliation: Comput. Sci. & Eng., Univ. of California, San Diego, La Jolla, CA, USA (Althoff, A.; Kastner, R.)
Abstract	Nonnegative least squares (NNLS) optimization is an important algorithmic component of many problems in science and engineering, including image segmentation, spectral deconvolution, and reconstruction of compressively sensed data. Each of these areas can benefit from high performance implementations suitable for embedded applications. Unfortunately, the NNLS problem has no solution expressible in closed-form, and many popular algorithms are not amenable to compact and scalable hardware implementation. Classical iterative algorithms generally have a per-iteration computational cost with cubic growth, and interdependencies which limit parallel approaches. In this paper we develop two efficient hardware architectures. One is based on a novel algorithm we develop in this paper specifically to reduce FPGA area consumption while preserving performance. We implement our architectures on a very small FPGA and apply them to reconstruction of a compressively sensed signal showing residual error results competitive with traditional algorithms.
Starting Page	1
Ending Page	8
File Size	594860
Page Count	8
File Format	PDF
ISBN	9780993428005
DOI	10.1109/FPL.2015.7293750
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-09-02
Publisher Place	UK
Access Restriction	Subscribed
Rights Holder	Imperial College
Subject Keyword	Hardware Field programmable gate arrays Convergence Algorithm design and analysis Random access memory Computer architecture Optimization compressive sensing FPGA nonnegative least squares nonnegative quadratic programming high-level synthesis
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework

An FPGA Memory Hierarchy for High-level Synthesized OpenCL Kernels

Hardware/software co-design using high level synthesis for cryptographic module

Novel hardware architecture of sparse recovery based on FPGAs

A parallel architecture for high speed BLAST using FPGA

Scalable Video Coding Deblocking Filter FPGA and ASIC Implementation Using High-Level Synthesis Methodology

Raising FPGA Logic Density Through Synthesis-Inspired Architecture

Scalable FPGA-based multiprocessor architecture for real-time embedded vision

FPGA Implementation of Orthogonal Matching Pursuit for Compressive Sensing Reconstruction

A scalable FPGA architecture for nonnegative least squares problems

Similar Documents

Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework

An FPGA Memory Hierarchy for High-level Synthesized OpenCL Kernels

Hardware/software co-design using high level synthesis for cryptographic module

Novel hardware architecture of sparse recovery based on FPGAs

A parallel architecture for high speed BLAST using FPGA

Scalable Video Coding Deblocking Filter FPGA and ASIC Implementation Using High-Level Synthesis Methodology

Raising FPGA Logic Density Through Synthesis-Inspired Architecture

Scalable FPGA-based multiprocessor architecture for real-time embedded vision

FPGA Implementation of Orthogonal Matching Pursuit for Compressive Sensing Reconstruction

A scalable FPGA architecture for nonnegative least squares problems