NDLI: From software threads to parallel hardware in high-level synthesis for FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Jongsok Choi Brown, S. Anderson, J.
Copyright Year	2013
Description	Author affiliation: ECE Dept., Univ. of Toronto, Toronto, ON, Canada (Jongsok Choi; Brown, S.; Anderson, J.)
Abstract	We describe the support within high-level hardware synthesis (HLS) for two standard software parallelization paradigms: Pthreads and OpenMP. Parallel code segments, as specified in the software, are automatically synthesized by our HLS tool into parallel-operating hardware sub-circuits. Both data parallelism and task-level parallelism are supported, as is the combined use of both Pthreads and OpenMP. Moreover, our work also provides automated synthesis for commonly occurring synchronization constructs within the Pthreads/OpenMP library: mutual exclusion (mutex) and barriers. Essentially, our framework allows a software engineer to specify parallelism to an HLS tool using methodologies they are likely to be familiar with. An experimental study considers a variety of parallelization scenarios, including demonstrated speedups of up to 12.9× in circuit wall-clock time for the 16-thread case and area-delay product as low as 12% (~8× improvement) when using 4 pipelined hardware threads.
Starting Page	270
Ending Page	277
File Size	284388
Page Count	8
File Format	PDF
e-ISBN	9781479921980
DOI	10.1109/FPT.2013.6718365
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-12-09
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Instruction sets Field programmable gate arrays Pipeline processing Synchronization
Content Type	Text
Resource Type	Article

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