NDLI: Scalable FPGA-based multiprocessor architecture for real-time embedded vision

Content Provider	IEEE Xplore Digital Library
Author	Samarawickrama, M. Rodrigo, R. Pasqual, A.
Copyright Year	2010
Description	Author affiliation: Department of Electronic and Telecommunication Engineering, University of Moratuwa, Sri Lanka (Samarawickrama, M.; Rodrigo, R.; Pasqual, A.)
Abstract	Real-time image processing demands much more processing power than a conventional processor can deliver. As a result hardware acceleration became necessary to augments processors with application-specific coprocessors. Due to the limited resources on FPGA and nature of some sequential algorithms, it is difficult to depend entirely on slice resources. In this research, we implemented a multiprocessor architecture to support real-time image processing on FPGA. Furthermore, we benchmarked and compared our implemented architectures with their counterparts. The operational structure of multiprocessor architecture consists of on-chip processors implemented in a parallel manner with efficient memory and bus architectures. The performance properties such as accuracy, throughput and efficiency are measured and presented. Multiprocessor systems are effective in software level parallelism on FPGA. Our quad-Microblaze architecture achieved 75–80% performance improvement compared to its single Microblaze counterpart. Moreover, the quad-Microblaze design is faster than the single-powerPC implementation on FPFA. Therefore, multi-processor architecture with customised coprocessors are effective for implementing custom parallel architecture to achieve real-time image processing.
Starting Page	172
Ending Page	176
File Size	279038
Page Count	5
File Format	PDF
ISBN	9781424485499
e-ISBN	9781424485529
DOI	10.1109/ICIAFS.2010.5715655
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-12-17
Publisher Place	Sri Lanka
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Real time systems PowerPC multi-processor real-time architecture FPGA Random access memory Process control cache optimization mutex memory configuration Computer architecture Hardware Software Microblaze Field programmable gate arrays
Content Type	Text
Resource Type	Article

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