NDLI: Block-Level Electro-Migration Analysis (BEMA) for Safer Product Life

Content Provider	IEEE Xplore Digital Library
Author	Gupta, Radhika Bhargava, Atul Panemangalore, Rakeshshenoy
Copyright Year	2015
Abstract	With technologies like Fully Depleted Silicon On Insulator (FDSOI), the high performance transistor devices push very good Ion but the metallization is not equipped to handle it reliably for different Power-on-Hours (POH) needs. Current density is not scaling down proportionally with downscaling and hence resulting into more stress on interconnects for these advanced nodes. Traditional method of running electro migration (EM) checks at the final stage of the Intellectual Property (IP) development cycle - after integration of all building blocks at the top level - becomes a complex and time consuming activity. This method has two basic challenges -- 1) Not scalable for large memory instances 2) Will take at least 2 man weeks per compiler. In this paper we present a new methodology of checking electro migration at the block level. This methodology is not restricted to Memories and can be applied to any Custom IP that is hierarchical and is developed top-down. This greatly reduces the effort needed to clean up electro migration and joule heating violations at the top level. The correlation between the full cut and block level results is within 2%. Running this analysis at block-level reduces any limit on the design size. Cumulative runtimes at block level turns out to be much smaller than a single run at the top level. This methodology saves us ~8X on the run time and ~14X on the total memory utilization. These gains are in addition to the fact that the product cycle time is reduced because we are able to run the analysis at an earlier stage where the corrections are practically possible.
Starting Page	276
Ending Page	281
File Size	350478
Page Count	6
File Format	PDF
ISBN	9781479966585
ISSN	10639667
DOI	10.1109/VLSID.2015.53
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-01-03
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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