NDLI: FPGA Based Scalable Fixed Point QRD Core Using Dynamic Partial Reconfiguration

Content Provider	IEEE Xplore Digital Library
Author	Prabhu, Gayathri R. Johnson, Bibin Rani, J. Sheeba
Copyright Year	2015
Abstract	This work presents an FPGA based scalable fixed point QRD architecture based on Givens Rotation algorithm. The proposed QRD core utilizes an efficient pipelined and unfolded 2D MAC based systolic array architecture with dynamic partial reconfiguration (DPR) capability. An improved LUT based Newton-Raphson method is proposed for finding square root and inverse square root which helps in reducing the area by 71% and latency by 50%, while operating at a frequency 49% higher than the existing boundary cell architectures. The scalability of the QRD core is achieved using DPR which results in reduction in dynamic power and area utilization as compared to a static implementation. The proposed architecture is implemented on Xilinx Virtex-6 FPGA for any real matrices of size m × n where, 4 ≤ n ≤ 8 and m ≥ n by dynamically inserting or removing the partial modules. The evaluation results shows reduction in latency, area and power as compared to CORDIC based architectures. The proposed scalable QRD core is used for implementing a high performance adaptive equalizer (QRD-RLS Algorithm) used in mobile receiver's and the evaluation is done by transmitting BPSK symbols in the training mode.
Starting Page	345
Ending Page	350
File Size	583897
Page Count	6
File Format	PDF
ISBN	9781479966585
ISSN	10639667
DOI	10.1109/VLSID.2015.64
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-01-03
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	LUT Newton Raphson QR decomposition Givens rotation Systolic array Partial reconfiguration
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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