NDLI: Tutorial T9: Dealing with Startup Issues in Low Power Mixed Signal SoCs

Content Provider	IEEE Xplore Digital Library
Author	Ganesan, S.
Copyright Year	2015
Abstract	Summary form only given. While most Silicon issues found in a complex Mixed Signal System On a Chip(SoC) usually result in a long debug, design fixing and verification cycles, having an unreliable startup arguably causes the most damaging impact in productizing the SoC. This is because such issues are not always be caught in the evaluation and characterization cycles of the SoC, but could show up at a much later stage, even after it has been released for production. The condition at which the chip fails to start up as intended, usually depends on a lot of variables such as temperature, power supply ramp up/down rates, leakage paths, substrate currents or even a strong RF field in the vicinity of the SoC. Due to this, the chances of catching the exact failure mechanism either through simulations during the design phase, or during lab testing phase is quite low. Therefore, the best way to deal with startup issues is to try and eliminate the possibility of such issues completely through robust design techniques. Considering the magnitude of the problem, it is very surprising to note that there is very little published literature on startup issues and on how to design to ensure robust startup. This tutorial is intended to bridge this gap. This tutorial on “Dealing with Startup-Issues in Low Power Mixed Signal SoCs” would be a Half-day tutorial divided into three parts each of length approximately one hour. First part of the tutorial would focus on startup circuit design self-biased reference circuits such as bandgap references focusing on ultra-low power. The second part would focus on simulation techniques to catch startup issues. The third and final part would focus on startup issues faced at full chip level and conclude with a check list to ensure robust startup. The tutorial would be in three parts each of duration one hour. In the first part of the tutorial, we will look at the classic analog startup problem associated with bandgap reference circuits and other such voltage or current reference circuits. The common pitfalls and weaknesses associated with the startup of these circuits would be highlighted. We will point to a number of published papers and patents with “flawed” startup circuits. We will highlight the challenges in implementing robust startup for ultra-low power reference circuits and look at the possibility of whether a zero -power circuit that can guarantee reliable startup is possible at all. In this regard we will also discuss the usage of Native-Vt devices in startup circuits and highlight the care one needs to take while using these devices in startup circuits. In the second part of the tutorial, we will describe simulation techniques by which we can catch many startup issues. We will discuss how to identify weaknesses in a startup circuit and to quickly figure out the PVT condition in which the circuit is most likely to have a startup failure. In this regard, we will discuss how we can check the robustness of the startup circuit by adding small leakage currents in certain select nodes in the circuit. The key idea here is to ascertain whether the circuit is starting up in the intended fashion with a guaranteed minimum current, or whether the startup is happening due to other unintended means. These include startup due to leakage currents getting mirrored around in a regenerative fashion, or due to capacitive coupling. Another simulation technique called “force-sense” which is similar to small signal loop gain analysis would be explained which can help catch the possibility of multiple operating points in the circuit. In the final part of the tutorial, we will discuss startup issues at a full chip and system level. Power On Reset (POR) circuit is the most important circuit in this regard and some of the common mistakes done during POR design would be highlighted. We will apply the same simulation techniques described above to probe for weaknesses in POR circuits. Just like startup circuits, we will discuss whether zero power POR circuits are possible at all and draw parallels between the two. We will then discuss how level shifters and “Tie cells”, which are often treated very casually by designers, could make or break the starting up of a chip. We will discuss power supply sequencing in multiple power rail systems and also highlight the care that one needs to take while implementing “soft start” and current limiting of linear regulators. It will be shown how these can cause a chip to fail to power up if not proper attention is not paid in the system design. We will conclude the tutorial with a check list of “Do's” and “Don'ts” for ensuring robust chip startup. The complete presentation was not made available for publication as part of the conference proceedings.
Sponsorship	VLSI
Starting Page	17
Ending Page	18
File Size	194579
Page Count	2
File Format	PDF
ISBN	9781479966585
ISSN	10639667
DOI	10.1109/VLSID.2015.117
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-01-03
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Tutorials Robustness System-on-chip Integrated circuit modeling Low-power electronics Very large scale integration Power supplies
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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