NDLI: Accelerating SVM on Ultra Low Power ASIP for High Throughput Streaming Applications

Content Provider	IEEE Xplore Digital Library
Author	Gupta, Anmol Pal, Ashutosh
Copyright Year	2015
Abstract	With increasing complexity of algorithms for embedded systems, demand for higher processor performance and lower battery power consumption is growing immensely. Due to upcoming fields like embedded vision where algorithms require learning, techniques like Support Vector Machines (SVM) have gained significant importance in these areas. These machines are required in performing classification tasks in variety of fields to analyze data, recognize patterns in images and videos. In this work, SVM is implemented on an Application Specific Instruction Processor (ASIP) designed using an Architectural Description Language (ADL) based tool to meet the ultra-high throughput and ultra-low power requirement posed by pedestrian detection algorithm in embedded vision-domain. We started with a base RISC processor and added a list of systematic extensions to gain speed for SVM like algorithms. With this we could achieve a throughput of ~630K SVMs/sec (~3k dimensions) at 6.5 mW, which is significantly better than GPU (Nvidia GTX280 at 236 Watt) in terms of power and ARM Cortex-A8 (~16K SVMs/sec) in terms of throughput.
Starting Page	517
Ending Page	522
File Size	486500
Page Count	6
File Format	PDF
ISBN	9781479966585
ISSN	10639667
DOI	10.1109/VLSID.2015.93
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-01-03
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	ASIP SVM
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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