NDLI: Two Phase Write Scheme to Improve Low Voltage Write-ability in Medium-Density SRAMs

Content Provider	IEEE Xplore Digital Library
Author	Sultan, M. Siddiqui, M. Sharad, Shailendra Sharma, Yogendra Khanuja, Amit
Copyright Year	2015
Abstract	State-of-art SRAM designs use either the negative bit line or the overdrive word line write assist circuits to improve the write-ability in a low voltage VDDMIN environment. But at the higher voltage operations, these write assist circuits will have an adverse effect on the SRAM bit cell's pass gate oxide tox reliability like hot carrier injection and time-dependent dielectric breakdown (TDDB). In this paper, we propose a novel two phase write scheme to improve the write-ability in a VDDMIN environment. We achieved improved write-ability by driving the word line voltage level to the power supply rail, in conjunction with the medium-sized SRAM bit cell. Simulation results at VDDMIN voltage of 0.52V in 16nm TSMC Fin FET technology, demonstrate that the worst 5σ bit cell write margin is improved by 85mV. Our two phase write scheme with the word line voltage level restricted to the power supply rail, does not risk the bit cell's pass gate tox reliability at the higher voltage operations. We also present the two phase write scheme macro implementation for a column multiplexed SRAM architecture.
Starting Page	176
Ending Page	180
File Size	196054
Page Count	5
File Format	PDF
ISBN	9781479966585
ISSN	10639667
DOI	10.1109/VLSID.2015.35
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-01-03
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Register files SRAM Write margin improvement Psuedo read SNM improvement Write cycle VDDMIN improvement
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in