NDLI: A 17.5-to-20.94GHz and 35-to-41.88GHz PLL in 65nm CMOS for wireless HD applications

Content Provider	IEEE Xplore Digital Library
Author	Richard, O. Siligaris, A. Badets, F. Dehos, C. Dufis, C. Busson, P. Vincent, P. Belot, D. Urard, P.
Copyright Year	2010
Description	Author affiliation: STMicroelectronics, Grenoble, France (Badets, F.) \|\| CEA-LETI-Minatec, Grenoble, France (Siligaris, A.; Dehos, C.; Vincent, P.) \|\| STMicroelectronics, Crolles, France (Richard, O.; Dufis, C.; Busson, P.; Belot, D.; Urard, P.)
Abstract	This work shows a complete PLL that is integrated in standard industrial 65nm CMOS technology. This frequency synthesizer is fully compliant with IEEE 802.15.3c normalization [1–4]. This PLL delivers a quadrature LO signal around 20GHz and a differential LO signal around 40GHz and has 17.9% tuning range. The wide tuning range of 17.9% permits to cover the full IEEE 802.15.3c band with industrial margin. The phase noise is −100dBc/Hz at 1MHz offset and the total power dissipation is only 80mW including the output buffers and amplifiers. Short-range wireless multi-Gb/sec communication systems use the mm-wave band of 57GHz to 66GHz, according to the IEEE 802.15.3c normalization. The frequency synthesis is one of the key elements for these transceivers. Indeed, one must take into account the antagonist tradeoff between large band tuning range of the frequency synthesizer and phase noise performance. In transceivers using super-heterodyne architecture with double conversion, the frequency synthesizer signal fLO can be equal to 2fRF /3 and fRF /3. In this case, to cover the four channels of the IEEE 802.15.3c normalization, the frequency synthesizer has to deliver a first local oscillator (LO) signal between 19.44GHz and 21.6GHz and a second LO signal between 38.88GHz and 43.2GHz, respectively. This architecture offers a good trade off between the required large frequency tuning range (≫15%) and low phase noise (≪−95dBc/Hz).
Starting Page	252
Ending Page	253
File Size	773034
Page Count	2
File Format	PDF
ISBN	9781424460335
ISSN	01936530
e-ISBN	9781424460366
DOI	10.1109/ISSCC.2010.5433941
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-02-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phase locked loops High definition video Frequency synthesizers Voltage-controlled oscillators Varactors Filters Voltage control Frequency conversion Phase frequency detector Semiconductor device measurement
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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