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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Spagna, F. Lidong Chen Deshpande, M. Yongping Fan Gambetta, D. Gowder, S. Iyer, S. Kumar, R. Kwok, P. Krishnamurthy, R. Chien-chun Lin Mohanavelu, R. Nicholson, R. Ou, J. Pasquarella, M. Prasad, K. Rustam, H. Tong, L. Tran, A. Wu, J. Xuguang Zhang |
| Copyright Year | 2010 |
| Description | Author affiliation: Intel, Santa Clara, CA, USA (Spagna, F.; Lidong Chen; Deshpande, M.; Gambetta, D.; Gowder, S.; Iyer, S.; Kumar, R.; Kwok, P.; Krishnamurthy, R.; Chien-chun Lin; Mohanavelu, R.; Nicholson, R.; Ou, J.; Pasquarella, M.; Prasad, K.; Rustam, H.; Tong, L.; Tran, A.; Wu, J.; Xuguang Zhang) || Intel, Hillsboro, OR, USA (Yongping Fan) |
| Abstract | The last few years have witnessed a rapid increase in serial IO data rates as well as number of IO ports in microprocessors. This trend, poses significant challenges to the serial IO design because of area and power budget limitations but, above all, by the need to achieve stringent bit error rates in the presence of interconnect constraints such as channel loss, impedance discontinuities induced by package and connectors, and crosstalk effects due to routing limitations in the package and on the motherboard. To effectively meet these challenges, the serial IO architecture has evolved to include more complex equalization schemes. Building on the previous work on a 4-tap DFE [1], this paper presents the design of a complete serial IO capable of operating up to 11.8Gb/s, and in particular, focuses on the integration of an adaptive equalizer and baud-rate CDR in the receiver of the serial IO. |
| Starting Page | 366 |
| Ending Page | 367 |
| File Size | 524194 |
| Page Count | 2 |
| File Format | |
| ISBN | 9781424460335 |
| ISSN | 01936530 |
| e-ISBN | 9781424460366 |
| DOI | 10.1109/ISSCC.2010.5433823 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-02-07 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Transceivers Adaptive equalizers Decision feedback equalizers Bit error rate Timing Integrated circuit interconnections Clocks Phase estimation Circuit testing LAN interconnection |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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