NDLI: A 45nm CMOS 13-port 64-word 41b fully associative content-addressable register file

Content Provider	IEEE Xplore Digital Library
Author	Burda, G. Kolla, Y. Dieffenderfer, J. Hamdan, F.
Copyright Year	2010
Description	Author affiliation: Qualcomm, Raleigh, NC, USA (Burda, G.; Kolla, Y.; Dieffenderfer, J.; Hamdan, F.)
Abstract	The high-performance needs of mobile products has motivated CPU designers to increase processing performance while decreasing power consumption. A dual-issue out-of-order superscalar ARMv7-architecture CPU uses the technique of register-renaming to resolve write-after-read and write-after-write data hazards associated with register file (RF) operands. Register-renaming increases processing throughput by increasing instruction parallelism through the avoidance of many hazard-induced pipeline stalls. The RF is a 64-word, 41-bit fully-associative content-addressable array with three CAM-write ports, four RAM-write ports, and six read ports. The RF incorporates many low-power circuit and micro-architectural techniques unseen in prior similar RFs [1,2], such as gated-xnor static comparators, tri-state floating read bitlines, and read wordline gating to prevent unnecessary RF reads.
Starting Page	286
Ending Page	287
File Size	1564976
Page Count	2
File Format	PDF
ISBN	9781424460335
ISSN	01936530
e-ISBN	9781424460366
DOI	10.1109/ISSCC.2010.5433924
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-02-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Radio frequency Registers Energy consumption Pipelines DH-HEMTs Circuits Read-write memory CMOS process Delay Logic
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A 256K dual port memory

A three-port adiabatic register file suitable for embedded applications

A 32b 64-word 9-read-port/7-write-port pseudo dual-bank register file using copied memory cells for a multi-threaded processor

A 14-port 3.8-ns 116-word 64-b read-renaming register file

A 14-port 3.8 ns 116-word 64b read-renaming register file

A 500 MHz, write-bypassed, 88-entry, 90-bit register file

A three-port nRERL register file for ultra-low-energy applications

Efficient Design of Shift Registers Using Reversible Logic

A low-power 8-read 4-write register file design

A 45nm CMOS 13-port 64-word 41b fully associative content-addressable register file

Similar Documents

A 256K dual port memory

A three-port adiabatic register file suitable for embedded applications

A 32b 64-word 9-read-port/7-write-port pseudo dual-bank register file using copied memory cells for a multi-threaded processor

A 14-port 3.8-ns 116-word 64-b read-renaming register file

A 14-port 3.8 ns 116-word 64b read-renaming register file

A 500 MHz, write-bypassed, 88-entry, 90-bit register file

A three-port nRERL register file for ultra-low-energy applications

Efficient Design of Shift Registers Using Reversible Logic

A low-power 8-read 4-write register file design

A 45nm CMOS 13-port 64-word 41b fully associative content-addressable register file