NDLI: A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment

Content Provider	IEEE Xplore Digital Library
Author	Nii, K. Yabuuchi, M. Tsukamoto, Y. Ohbayashi, S. Oda, Y. Usui, K. Kawamura, T. Tsuboi, N. Iwasaki, T. Hashimoto, K. Makino, H. Shinohara, H.
Copyright Year	2008
Description	Author affiliation: Renesas Technol. Corp., Tokyo (Nii, K.; Yabuuchi, M.; Tsukamoto, Y.; Ohbayashi, S.)
Abstract	We propose an enhanced design solution for embedded SRAM macros under dynamic voltage and frequency scaling (DVFS) environment. The improved wordline suppression technique using replica cell transistors and passive resistances compensates the read stability against process variation, facilitating the Fab. portability. The negative bitline technique expands the write margin for not only 6T single-port (SP) cell but also 8T dual-port (DP) cell even at the 0.7 V lower supply voltage. Using 45-nm CMOS technology, we fabricated both SP and DP SRAMs with the proposed circuitry. We achieve robust operations from 0.7 V to 1.3 V wide supply voltage.
Starting Page	212
Ending Page	213
File Size	525676
Page Count	2
File Format	PDF
ISBN	9781424418046
DOI	10.1109/VLSIC.2008.4586011
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-06-18
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Robustness Voltage measurement Thermal stability CMOS integrated circuits Circuit stability Integrated circuit modeling stability SRAM DVFS 6T 8T 45nm CMOS
Content Type	Text
Resource Type	Article

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