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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Walder, J.P. Denes, P. Grace, C. von der Lippe, H. Zheng, B. |
| Copyright Year | 2011 |
| Description | Author affiliation: Lawrence Berkeley National Laboratory, CA 94720 USA (Walder, J.P.; Denes, P.; Grace, C.; von der Lippe, H.; Zheng, B.) |
| Abstract | A fast, low noise charge sensitive preamplifier for column parallel CCD readout application is presented. This prototype has been implemented on a commercial CMOS 65nm process. This preamplifier consists of a two stage transconductance amplifier with capacitive feedback to accommodate two gain ranges and a second transconductance amplifier to reset the circuit. An equivalent noise charge of 37 electrons for a 100ns readout cycle time is achieved for a power consumption of 5mW. Novel design techniques used in this circuit will be presented in detail along with measurement results obtained on the prototype. |
| Starting Page | 721 |
| Ending Page | 724 |
| File Size | 1710354 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781467301183 |
| ISSN | 10823654 |
| e-ISBN | 9781467301206 |
| DOI | 10.1109/NSSMIC.2011.6154090 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-10-23 |
| Publisher Place | Spain |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Linearity |
| Content Type | Text |
| Resource Type | Article |
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