NDLI: FPGA implementation of marginalized particle filter for sensorless control of PMSM drives

Content Provider	IEEE Xplore Digital Library
Author	Smidl, V. Nedved, R. Kosan, T. Peroutka, Z.
Copyright Year	2013
Description	Author affiliation: Regional Innovation Centre for Electr. Eng., Univ. of West Bohemia, Pilsen, Czech Republic (Smidl, V.; Nedved, R.; Kosan, T.; Peroutka, Z.)
Abstract	Marginalized particle filter is a stochastic filter combining Kalman filters with particle filters. It decomposes the model into linear and nonlinear part and applies the Kalman filter for the former and the particle filter for the latter. In effect, this allows to represent accurately the inherent non-Gaussianity and nonlinearity of the model. This allows estimation of the rotor position of the PMSM drive in the full speed range, including the standstill. The main disadvantage is its high computational cost. In this paper, we present an implementation of the marginalized particle filter in the field programmable logic array (FPGA). The parallel nature of the MPF algorithm allows to use pipelining which yields speedup in the order of magnitude in comparison to the DSP implementation. The sensorless control of the drive is implemented on a board with both DSP and FPGA, where the drive control runs on the DSP and the MPF estimator in the FPGA. Execution time of the estimator is thus negligible in the execution time of the sensorless control. Performance of the resulting sensorless control algorithm is evaluated on a developed drive prototype of rated power of 10.7kW.
Sponsorship	IEEE Ind. Electron. Soc.
Starting Page	8227
Ending Page	8232
File Size	741743
Page Count	6
File Format	PDF
ISBN	9781479902248
ISSN	1553572X
DOI	10.1109/IECON.2013.6700510
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-11-10
Publisher Place	Austria
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Rotors Field programmable gate arrays Digital signal processing Mathematical model Kalman filters Sensorless control Pipelines
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in