NDLI: Optimal low switching frequency pulsewidth modulation of medium voltage seven-level cascade-5/3H inverter

Content Provider	IEEE Xplore Digital Library
Author	Edpuganti, A. Rathore, A.K.
Copyright Year	2013
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore, Singapore, Singapore (Edpuganti, A.; Rathore, A.K.)
Abstract	This paper presents the operation of seven-level inverter at maximum switching frequency of 75 Hz using synchronous optimal pulsewidth modulation (SOP). Employing SOP permits increasing efficiency by reducing switching losses of power semiconductor devices without compromising on total harmonic distortion (THD). A cascade-5/3H inverter topology is adapted used due to limitations of diode-clamped and capacitor-clamped topologies for higher-level inverters. SOP technique derives optimal switching angles for minimizing the THD and later seven-level waveforms are divided into 3-level and 5-level waveforms for cascade-5/3H topology so as to minimize the switching frequency and DC-link voltage unbalance. Simulation results of seven-level inverter using PSIM 9.0 operating at maximum device switching frequency of 75 Hz are shown to validate the developed modulation.
Sponsorship	IEEE Ind. Electron. Soc.
Starting Page	6287
Ending Page	6292
File Size	1987993
Page Count	6
File Format	PDF
ISBN	9781479902248
ISSN	1553572X
DOI	10.1109/IECON.2013.6700169
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-11-10
Publisher Place	Austria
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Inverters Switches Topology Switching frequency Optimization Pulse width modulation Harmonic analysis
Content Type	Text
Resource Type	Article

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