NDLI: Improving Efficiency of IC Burn-In Testing

Content Provider	IEEE Xplore Digital Library
Author	Yong Han Ng Yew Hock Low Demidenko, S.
Copyright Year	2008
Description	Author affiliation: Freescale Semicond., Petaling Jaya (Yong Han Ng; Yew Hock Low)
Abstract	Burn-in (i.e., electronic test performed under elevated temperature and other stress conditions) plays an important role in integrated circuits (ICs) manufacturing process to ensure required high quality and reliability of the produced semiconductors before shipping them to final users. Burn-in aims at accelerating detection and screening out of so-called 'infant mortalities' (early-life latent failures). It is normally associated with lengthy test time and high cost, often making it a bottleneck of the entire IC manufacturing process. It is no surprise therefore, that much attention and efforts have been dedicated towards possible ways of improving efficiency of the entire burn-in process. This paper looks at improving efficiency of practical burn-in testing process in the IC fabrication setting. The paper presents development of applied algorithms and relevant embedded software the burn-in and binning processes automation. In addition to the improved burn-in test efficiency, the developed tools lead also to yield improvement by providing more comprehensive test results data logging and analysis.
Starting Page	1685
Ending Page	1689
File Size	4138886
Page Count	5
File Format	PDF
ISBN	9781424415403
ISSN	10915281
DOI	10.1109/IMTC.2008.4547315
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-05-12
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Integrated circuit testing Circuit testing Manufacturing processes Electronic equipment testing Semiconductor device testing Performance evaluation Temperature Stress Integrated circuit reliability Semiconductor device reliability data logging burn-in electronic testing binning
Content Type	Text
Resource Type	Article
Subject	Instrumentation Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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