NDLI: How to bridge the abstraction gap in system level modeling and design

Content Provider	IEEE Xplore Digital Library
Author	Bernstein, A. Burton, M. Ghenassia, F.
Copyright Year	2004
Description	Author affiliation: Intel Corp., Haifa, Israel (Bernstein, A.)
Abstract	As more and more processors and subsystems are integrated in a single system, the verification bottleneck is driving designers away from RTL and RTL-like strategies for verification and design to higher abstraction levels. Increasing system complexity at the other hand requires much faster simulation and analysis tools. This is leading to new standards and tools around transaction level modeling. Languages such as SystemC and SystemVerilog are rich in behavioral and structural constructs which enable modeling designs at different levels of abstraction without imposing a top-down or bottom-up design flow. In fact, most design flows are iterative and modules at different levels of abstractions have to be considered. A more abstract model is very useful to increase simulation speed and to improve formal verification. SystemC and SystemVerilog stress the importance of verification support for complex SOCs including improvement for hardware verification as well as for the verification of hardware dependent software. In todays design flows the software development can often only start after the hardware is available. This causes unacceptable delays for the software development. The idea of transaction level modeling (TLM) is to provide in an early phase of the hardware development transaction level models of the hardware. Based on these TLMs a fast enough simulation environment is the basis for the development of hardware and hardware dependent software. The presumption is to run these transaction level models at several tens or some hundreds of thousand transactions per second which should be fast enough for system level modeling and verification.
Starting Page	910
Ending Page	914
File Size	366594
Page Count	5
File Format	PDF
ISBN	0780387023
ISSN	10923152
DOI	10.1109/ICCAD.2004.1382705
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-11-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Bridges Hardware Programming Costs Application software Product development Analytical models Formal verification Stress Software design
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Software

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