NDLI: Power estimation for cycle-accurate functional descriptions of hardware

Content Provider	IEEE Xplore Digital Library
Author	Lin Zhong Ravi, S. Raghunathan, A. Jha, N.K.
Copyright Year	2004
Description	Author affiliation: Dept. of Electr. Eng., Princeton Univ., NJ, USA (Lin Zhong)
Abstract	Cycle-accurate functional descriptions (CAFD) are being widely adopted in integrated circuit (IC) design flows. Power estimation can potentially benefit from the inherent increase in simulation efficiency of cycle-based functional simulation. Currently, most approaches to hardware power estimation operate at the register-transfer level (RTL), or lower levels of design abstraction. Attempts at power estimation for functional descriptions have suffered from poor accuracy because the design decisions performed during their synthesis lead to an unavoidable, large uncertainty in any power estimate that is based solely on the functional description. We propose a methodology for CAFD power estimation that combines the accuracy achieved by power estimation at the structural RTL with the efficiency of cycle-accurate functional simulation. We achieve this goal by viewing a CAFD as an abstraction of a specific, known RTL implementation that is synthesized from it. We identify correlations between a CAFD and its RTL implementation, and "back-annotate" information into the CAFD solely for the purpose of power estimation. The resulting RTL-aware CAFD contains a layer of code that instantiates virtual placeholders for RTL components, and maps values of CAFD variables into the RTL components' inputs/outputs, thus enabling efficient and accurate power estimation. Power estimation is performed in our methodology by simply co-simulating the RTL-aware CAFD with a simulatable power model library that contains power macro-models for each RTL component. We present techniques to further improve the speed of CAFD power estimation, through the use of control state-based adaptive power sampling. We have implemented and evaluated the proposed techniques in the context of a commercial C-based hardware design flow. Experiments with a number of large industrial designs (up to 1 million gates) demonstrate that the proposed methodology achieves accuracy very close to RTL power estimation with two-to-three orders of magnitude speedup in estimation times.
Starting Page	668
Ending Page	675
File Size	750228
Page Count	8
File Format	PDF
ISBN	0780387023
ISSN	10923152
DOI	10.1109/ICCAD.2004.1382659
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-11-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Circuit simulation Adaptive control Libraries State estimation Programmable control Sampling methods System-level design Space exploration Complexity theory
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

RTL-Aware Cycle-Accurate Functional Power Estimation

Power Estimation for Cycle-Accurate Functional Descriptions of Hardware (2004)

Power Estimation for Cycle-Accurate Functional Descriptions of Hardware (2004)

RTL-aware Cycle-Accurate Functional Power Estimation

Design space exploration for a UMTS front-end exploiting analog platforms

System level design with SPADE: an M-JPEG case study

A High-level Interconnect Power Model for Design Space Exploration

Accurate energy breakeven time estimation for run-time power gating

A Prototype-Based Gate-Level Cycle-Accurate Methodology for SoC Performance Exploration and Estimation

Power estimation for cycle-accurate functional descriptions of hardware

Similar Documents

RTL-Aware Cycle-Accurate Functional Power Estimation

Power Estimation for Cycle-Accurate Functional Descriptions of Hardware (2004)

Power Estimation for Cycle-Accurate Functional Descriptions of Hardware (2004)

RTL-aware Cycle-Accurate Functional Power Estimation

Design space exploration for a UMTS front-end exploiting analog platforms

System level design with SPADE: an M-JPEG case study

A High-level Interconnect Power Model for Design Space Exploration

Accurate energy breakeven time estimation for run-time power gating

A Prototype-Based Gate-Level Cycle-Accurate Methodology for SoC Performance Exploration and Estimation

Power estimation for cycle-accurate functional descriptions of hardware