NDLI: Analog performance space exploration by Fourier-Motzkin elimination with application to hierarchical sizing

Content Provider	IEEE Xplore Digital Library
Author	Stehr, G. Graeb, H. Antreich, K.
Copyright Year	2004
Description	Author affiliation: Inst. for Electron. Design Autom., TU Munich, Germany (Stehr, G.; Graeb, H.; Antreich, K.)
Abstract	Analog performance space exploration identifies the range of feasible performance values of a given circuit topology. It is an extremely challenging task of great importance to topology selection and hierarchical sizing. In this paper, a novel technique for the efficient simulation-based exploration of high-dimensional performance spaces is presented. To this end, fundamental circuit design knowledge is described by constraint functions. Based on a linearization of the latter and of the circuit performance functions, a description of the feasible performance range in the form of a polytope is derived. Moreover, the approach is integrated into a hierarchical sizing method, where it propagates topological and technological constraints bottom-up. Practical application results demonstrate the efficiency and usefulness of the new method.
Starting Page	847
Ending Page	854
File Size	601323
Page Count	8
File Format	PDF
ISBN	0780387023
ISSN	10923152
DOI	10.1109/ICCAD.2004.1382693
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-11-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Space exploration Circuit topology Circuit simulation Space technology Electronic design automation and methodology Circuit synthesis Circuit optimization Integrated circuit technology Engines Nonlinear equations
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Software

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