NDLI: DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs

Content Provider	IEEE Xplore Digital Library
Author	Chen, D. Cong, J.
Copyright Year	2004
Description	Author affiliation: Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA (Chen, D.; Cong, J.)
Abstract	In This work we study the technology mapping problem for FPGA architectures to minimize chip area, or the total number of lookup tables (LUTs) of the mapped design, under the chip performance constraint. This is a well-studied topic and a very difficult task (NP-hard). The contributions of This work are as follows: (i) we consider the potential node duplications during the cut enumeration/generation procedure so the mapping costs encoded in the cuts drive the area-optimization objective more effectively; (ii) after the timing constraint is determined, we will relax the non-critical paths by searching the solution space considering both local and global optimality information to minimize mapping area; (iii) an iterative cut selection procedure is carried out that further explores and perturbs the solution space to improve solution quality. We guarantee optimal mapping depth under the unit delay model. Experimental results show that our mapping algorithm, named DAOmap, produces significant quality and runtime improvements. Compared to the state-of-the-art depth-optimal, area minimization mapping algorithm CutMap (Cong and Hwan, 1995), DAOmap is 16.02% better on area and runs 24.2X faster on average when both algorithms are mapping to FPGAs using LUTs of five inputs. LUTs of other inputs are also used for comparisons.
Starting Page	752
Ending Page	759
File Size	670357
Page Count	8
File Format	PDF
ISBN	0780387023
ISSN	10923152
DOI	10.1109/ICCAD.2004.1382677
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-11-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Design optimization Field programmable gate arrays Algorithm design and analysis Table lookup Cost function Timing Delay Iterative algorithms Runtime Minimization methods
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Software

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