NDLI: Formal derivation of optimal active shielding for low-power on-chip buses

Content Provider	IEEE Xplore Digital Library
Author	Ghonemia, M. Ismail, Y.
Copyright Year	2004
Description	Author affiliation: Dept. of ECE, Northwestern Univ., Evanston, IL, USA (Ghonemia, M.; Ismail, Y.)
Abstract	Passive shielding has been used to reduce capacitive coupling effects of adjacent bus lines by inserting passive ground or power lines (shields) between the bus lines. Active shielding is another shielding technique, in which the shield is allowed to switch depending on the switching pattern of its adjacent bus lines. This work formally derives the optimal active shielding logic function for minimum power dissipation. It is also shown that this optimal active shielding architecture depends on the ratio of coupling to ground capacitance (/spl gamma/ = C/sub c//C/sub g/). Optimal active shielding is shown to provide up to 25% reduction in bus power dissipation compared to conventional passive shielding. A sub-optimal active shielding architecture with simpler hardware is also proposed. Simulation results show that using the sub-optimal shielding architecture leads to less than 6% bus power penalty compared to the optimal active shielding logic circuit.
Starting Page	800
Ending Page	807
File Size	506249
Page Count	8
File Format	PDF
ISBN	0780387023
ISSN	10923152
DOI	10.1109/ICCAD.2004.1382685
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-11-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Switches Capacitance Power dissipation Integrated circuit interconnections Delay Logic functions Circuit simulation Wires Hardware Logic circuits
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Formal derivation of optimal active shielding for low-power on-chip buses

Formal derivation of optimal active shielding for low-power on-chip buses.

Optimal Memoryless Encoding for Low Power Off-Chip Data Buses

A Timing Dependent Power Estimation Framework Considering Coupling

RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction

Optimum positioning of interleaved repeaters in bidirectional buses

Optimal permutation and spacing for unbiased random, counter, and instruction address buses

Efficient Insertion of Crosstalk Shielding along On-Chip Interconnect Trees

Crosstalk energy reduction by temporal shielding

Formal derivation of optimal active shielding for low-power on-chip buses

Similar Documents

Formal derivation of optimal active shielding for low-power on-chip buses

Formal derivation of optimal active shielding for low-power on-chip buses.

Optimal Memoryless Encoding for Low Power Off-Chip Data Buses

A Timing Dependent Power Estimation Framework Considering Coupling

RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction

Optimum positioning of interleaved repeaters in bidirectional buses

Optimal permutation and spacing for unbiased random, counter, and instruction address buses

Efficient Insertion of Crosstalk Shielding along On-Chip Interconnect Trees

Crosstalk energy reduction by temporal shielding

Formal derivation of optimal active shielding for low-power on-chip buses