NDLI: Bed of nails: fine pitch wafer-level packaging interconnects for high performance nano devices

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2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)

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2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)

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2010 12th Electronics Packaging Technology Conference

2009 11th Electronics Packaging Technology Conference

2008 10th Electronics Packaging Technology Conference

2007 9th Electronics Packaging Technology Conference

2006 8th Electronics Packaging Technology Conference

2005 7th Electronic Packaging Technology Conference

Volume 2 - 2005

Conference committee

Table of contents

Multistack flip chip 3D packaging with copper plated through-silicon vertical interconnection

Direct metal to metal bonding for microsystems interconnections and integration

Error proof inkless die bonding process development

Reliability of Cu/low-k wafer level package (WLP)

Simulation methodologies for electromagnetic compatibility (EMC) and signal integrity (SI) for system design

Radiation from arbitrary shape power/ground plane pair structure

Electromagnetic susceptibility analysis of high speed circuit inside the shielding enclosure with an aperture

A model for efficient and improved measurements of the complex permittivity of thin organic packaging materials using open-ended coaxial line technique

Investigation of IMC layer effect on PBGA solder joint thermal fatigue reliability

Improved slim sector model for analysis of solder joint reliability

Solder joint fatigue in a surface-mount assembly subjected to mechanical loading

Simulation-based design optimization of solder joint reliability of wafer level copper column interconnects

Impact of drop-in lead free solders on microelectronics packaging

Stress effect on growth of IMCs at interfaces between Sn-Ag-Cu lead free solder and Cu substrate

Fabrication process for high-density wiring interposer using photosensitive multiblock copolyimide insulation layers for 3D packaging

Solder joint integrity of various surface finished build-up flip chip packages by 4-point monotonic bending test

Polymer based optical interconnect module for a bidirectional transceiver and optical N/spl times/M star couplers for datacom applications with data rates > 1Gbps

Manufacture of two-dimensional monomode optical fiber array using MEMS technology

Fabrication of low-cost panel sized optical-printed circuit boards

Prototype development for chip-chip interconnection by multimode waveguide

Influence of solder volume on interfacial reaction between Sn-Ag-Cu solder and TiW/Cu/Ni UBM

Process characteristics of 100 /spl mu/m bump pitch with lead-free and high lead plating solder bump

Influence of phosphorus content on the interfacial microstructure between Sn-3.5Ag solder and electroless Ni-P metallization on Cu substrate

Development of fine pitch solders joint interconnection technology for flip chip assembly

Failure analysis of sub-50 /spl mu/m lead-free solder bumps on electroless Ni-P UBM for flip chip interconnects

Thermal modelling of multiple die packages

Effect of solder voids on thermal performance of a high power electronic module

TIM characterization for high performance microprocessors

Qualification of phase change thermal interface material for wave solder heat sink on FCBGA package

Thermal analysis and experimental validation on TFT-LCD panels for image quality concerns

Influence of non-uniform initial porosity distribution on adhesive failure in electronic packages

Application of modified virtual crack closure method on delamination analysis in a plastic IC package during lead-free solder reflow

Characterization and modeling of hygroscopic swelling and its impact on failures of a flip chip package with no-flow underfill

Non-linear finite element analysis for electronic packages subjected to combined hygroscopic and thermo-mechanical stresses

Comprehensive analysis of a larger die, copper pillar bump flip chip package with no-flow underfill

Investigating effect of unfilled underfills on board level solder joint reliability of area array packages under drop test and thermal cycling test

Intermetallic growth behaviour of gold ball bonds encapsulated with green moulding compounds

Effects of mask patterns optimization and silicon surface preparation for anisotropic silicon etching

Coprecursor approach to the fabrication of superhydrophobic durable self-cleaning films

High temperature storage (HTS) performance of copper ball bonding wires

Reliability and thermal structure design for CMOS image sensor

Coarsening processes in the lead-free solder alloy AgCu: theoretical and experimental investigations

Effects of thermal, moisture and mechanical loading conditions on interfacial fracture toughness using Brazil-nut specimens

Quantitative reliability analysis of electronic packages in consideration of variability of model parameters

High-G drop impact response and failure analysis of a chip packaged printed circuit board

Electroless plating of nickel on carbon nanotubes film

Low temperature fluxless technology for ultra-fine pitch and large devices flip-chip bonding

Growth of aligned carbon nanotube arrays for electrical interconnect

Ultrathin assemblies on flexible substrates

Bed of nails: fine pitch wafer-level packaging interconnects for high performance nano devices

Experimental study of a radial micro-channel cooling plate

Experimental characterization of flow boiling heat dissipation in a microchannel heat sink with different orientations

Passive two-phase cooling solution with a novel heat transfer enhancement technique for electronic packages

Spherical boron nitride fillers for high performance thermal greases

Development of ball grid array packages with improved thermal performance

Considerations for minimizing radiation doses to components during X-ray inspection

A novel polishing mechanism used in manufacturing ultra-high uniformity gold solder bump

PEDL (polymer encapsulated dicing line) technology for copper/low-k dielectrics interconnect

Process technique for singulating fragile devices

Reducing the effect of mechanical stress on low-k die - case study

Development of high performance photo-curable nanocomposites for electronics packaging

Mechanism of underfill voids formation in flip chip packaging

Bubbles formation in rigid-flexible substrates bonding using anisotropic conductive films (ACFs) and their effects on ACFs joints reliability

Dielectric properties in thin film SrTiO/sub 3/ capacitor

Post-curing influence on electrostatic charges deposited on epoxy/silica composites used for microelectronic packaging

Feasibility study on board assembly of TSSOP components with NiPdAu PPF finish

Effects of lead design on ultrasonic bond quality of wire bonds

Improving the solder joint reliability of VQFN packages

Effects of re-finishing of terminations by solder-dipping on plastic quad flatpack electronic parts

The reliability of isotropically conductive adhesive as solder replacement - a case study using LCP substrate

Bonding development for non-conductive paste (NCP)

Electromigration reliability of Sn-37Pb and Sn-3Ag-1.5Cu/Sn-3Ag-0.5Cu composite flip-chip solder bumps with Ti/Ni(V)/Cu under bump metallurgy

A study of ultrasonic bonding of minute Au bumps

Influence of bump geometry, adhesives and pad finishings on the joint resistance of Au bump and A/NCA flip chip interconnection

Fabrication of thermoelectric cooler for device integration

The more accurate method to extract dielectric constant and loss tangent of insulated material on microwave frequencies

Data-dependent jitter estimation using single pulse analysis method

An improved low-cost 6.4 Gbps wafer-level tester

Design practices and issues for simultaneous switching noise

EMI simulation and measurements of multilayer structures for microprocessor packaging applications

High performance conductive adhesives modified with molecular wires

Dispensing solder paste micro-deposits to 0.2mm - a process solution

Thermal and mechanical behaviors of underfills for flip-chip packaging

Die attach film application in multi die stack package

Integrated shadow mask for full angle deposition in fabrication of passive matrix OLED displays

Impact of fatigue modeling on 2/sup nd/ level joint reliability of BGA packages with SnAgCu solder balls

Interfacial IMC and Kirkendall void on SAC solder joints subject to thermal cycling

Bend fatigue reliability test and analysis for Pb-free solder joint

Effect of Ni-P thickness on the tensile strength of Cu/electroless Ni-P/Sn-3.5Ag solder joint

Volume 1 - 2005

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)

Proceedings of the 5th Electronics Packaging Technology Conference (EPTC 2003)

4th Electronics Packaging Technology Conference, 2002.

Proceedings of 3rd Electronics Packaging Technology Conference (EPTC 2000) (Cat. No.00EX456)

Proceedings of 2nd Electronics Packaging Technology Conference (Cat. No.98EX235)

Proceedings of the 1997 1st Electronic Packaging Technology Conference (Cat. No.97TH8307)

Bed of nails: fine pitch wafer-level packaging interconnects for high performance nano devices

Content Provider	IEEE Xplore Digital Library
Author	Rao, Vempati Srinivasa Kripesh, V. Seung Wook Yoon Witarsa, D. Tay, A.A.O.
Copyright Year	2005
Description	Author affiliation: Inst. of Microelectron., Singapore (Vempati Srinivasa Rao; Kripesh, V.; Seung Wook Yoon; Witarsa, D.)
Abstract	The rapid advances in IC design and fabrication continue to challenge electronics packaging technology in terms of fine pitch, high performance, low cost and better reliability. The shift towards the nano ICs with feature size less than 90nm, increases the demand for higher I/O count per integrated circuit (IC) chip. The demands for high pin count and the increasing packaging density requirements in high performance device packaging is necessitating less than 100 microns pitch chip to substrate interconnection technologies. However, the long-term board level reliability of packages with large distance from neutral point (DNP) is not yet fully solved. Wafer level packaging is the promising solution to meet the cost and fine pitch requirements. Currently, the CTE mismatch between Si chip and substrate serves as the biggest bottleneck in the conventional chip-to-substrate interconnection technology and this becomes even more critical with reduction in pitch of the interconnects. Added to this, even the assembly yield of such fine pitch interconnections also serves as one of the other biggest challenges. In this paper, the bed of nails (BoN) interconnection technology on a 20 times 20 $mm^{2}$ test chip with 2256 and 36,481 I/Os in 3 depopulated rows and fully populated, respectively, are presented. This technology has been developed to achieve a fine pitch of 100 microns and high density interconnections. The test demonstrators are designed with same number of I/Os and fabricated. Compliance is also provided by giving high stand-off height of interconnect ( > 2 aspect ratio) compared to the conventional solder bumping where the aspect ratio equals one. The board level reliability test is performed on the 20 times 20 $mm^{2}$ test chip with depopulated BoN interconnects, with and without underfill, under temperature cycling at the range of -400degC to 125degC
File Size	4695894
File Format	PDF
ISBN	0780395786
DOI	10.1109/EPTC.2005.1614483
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-12-07
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Nails Wafer scale integration Integrated circuit interconnections Testing Integrated circuit packaging Electronics packaging Integrated circuit technology Costs Integrated circuit reliability Fabrication
Content Type	Text
Resource Type	Article

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