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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Vijayaragavan, N. Carson, F. Mistry, A. |
| Copyright Year | 2008 |
| Description | Author affiliation: Spansion Inc., Sunnyvale, CA (Vijayaragavan, N.) |
| Abstract | The need to integrate devices in the vertical dimension to reduce space, thickness, and cost for handheld applications has fueled the enormous growth of what can be termed 3D packaging. Due to testability, business flow, and configuration flexibility issues, the package on package (PoP) vertical stacking solution has emerged as the preferred method to stack mobile phone logic processor with memory. The PoP solution typically consists of the logic processor in the bottom package and memory device stack in the top package. The bottom PoP has land pads on the top perimeter in order to allow top PoP to be mounted and reflowed above. Both packages must be capable of being placed on the printed circuit board (PCB) and reflowed simultaneously to each other and to the board. Hence the warpage of the top and bottom PoP relative to each other becomes critical in impacting board mount yields and adoption. This paper presents a systematic study performed to modulate the warpage of the top as well as the bottom PoP and study the effect of the relative warpage of the top and bottom PoP on surface mount (SMT) yields during PoP assembly. A 15times15 mm POP module was selected for this study. This package size represents the higher side of the typical package size spectrum for PoP applications and hence the warpage effects are also magnified. Shadow Moire technique was used for high temperature warpage measurement while subjecting the test samples to a simulated reflow profile. The results of this study can be used as a reference by original equipment manufacturers (OEMs) to define warpage limits to ensure a robust SMT POP stacking yield and board level reliability of the POP module. Further, it can used by integrated device manufacturers (IDMs) and packaging subcontractors to determine the kind of material set and construction required to meet specific warpage targets and be compatible with the other package in the PoP stack. This represents a significant advancement over the current practice of procuring the top and bottom packages manufactured independent of each other and reactively dealing with SMT yield issues. |
| Starting Page | 389 |
| Ending Page | 396 |
| File Size | 1471548 |
| Page Count | 8 |
| File Format | |
| ISBN | 9781424422302 |
| ISSN | 05695503 |
| DOI | 10.1109/ECTC.2008.4550001 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-05-27 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Surface-mount technology Manufacturing Logic testing Stacking Logic devices Packaging machines Temperature measurement Costs Mobile handsets Printed circuits |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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