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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Tsrong-Yi Wen Shih-Chang Ku |
| Copyright Year | 2008 |
| Description | Author affiliation: VIA Technol., Inc., Taipei (Tsrong-Yi Wen; Shih-Chang Ku) |
| Abstract | Warpage of organic flip chip ball grid array (FCBGA) package during IR-reflow results from mismatch of componential coefficient of thermal expansion (CTE). It is distinctly affected by complex factors such as material selection, geometry or manufacturing process [1]. Within this study, a four-layer (1-2-1) 21times21 mm organic substrate with 4.95times7.30 mm silicon die and two different dispensing lengths of underfill are cited. This presentation will demonstrate the mechanical behavior, i.e. warpage, by finite element method with efficient technique. Shadow moire is an in-situ, full field, and high precision optical metrology for measuring the out- of-plane displacement and is conducted for correlation between simulation and experiment. The results show that simulation is in good agreement with experiment for warpage of small 21times21 mm flip-chip package under various temperature stages. Base on the correlation, we will perform parametric study to provide a design reference by a scientific and statistic way. Therefore, analysis of variance (ANOVA) is brought up. Stack-up layer thicknesses of substrate and dispensing length of underfill are selected for 2 level factorial designs and result in 29 simulation runs. Through ANOVA analysis, thickness of central copper trace layer, dielectric layer are the most major factor which has dramatic effect on the warpage and its direction as temperature elevation. Following are top solder mask layer and dispensing length of underfill. Nevertheless, in point of process, the dispensing length of underfill is relatively controllable compared to other processes in IC packaging such as substrate tolerance. On the other hand, six key features, include dimension of substrate, thickness of substrate core, dispensing length of underfill, type of underfill, bump height and thickness of silicon die are discussed. Among reasonable and production specification, dispensing length of underfill is the most important through these six factors. |
| Starting Page | 1587 |
| Ending Page | 1592 |
| File Size | 613050 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424422302 |
| ISSN | 05695503 |
| DOI | 10.1109/ECTC.2008.4550188 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-05-27 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Analysis of variance Silicon Temperature Dielectric substrates Flip chip Electronics packaging Thermal expansion Geometry Manufacturing processes Finite element methods |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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