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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Selvanayagam, C.S. Lau, J.H. Xiaowu Zhang Seah, S.K.W. Vaidyanathan, K. Chai, T.C. |
| Copyright Year | 2008 |
| Description | Author affiliation: Inst. of Microelectron., Agency for Sci., Technol., & Res., Singapore (Selvanayagam, C.S.; Lau, J.H.; Xiaowu Zhang; Seah, S.K.W.; Vaidyanathan, K.; Chai, T.C.) |
| Abstract | Most of TSVs are filled with the copper, even siliconpoly and tungsten are the alternatives. The coefficient of thermal expansion (CTE) of copper $(~17.5x10^{-6}/degC)$ is a few times higher than that of silicon $(~2.5x10^{-6}/degC).$ Thus, when the copper filled TSV is subjected to temperature loadings, there is a very large local thermal expansion mismatch between the copper and the silicon/dielectric (e.g., $SiO_{2}),$ which will create very large stresses and strains at the interfaces between the copper and the silicon and between the copper and the dielectric. These stresses/strains can be high enough to introduce delamination between the interfaces. In this study, the nonlinear thermal stresses and strains at the interfaces between the copper, silicon, and dielectric have been determined for a wide-range of aspect ratios (of the silicon thickness and the TSV diameter). One of the major applications of TSV is as an interposer. Because of Moore's (scaling/integration) law, the silicon chip is getting bigger, the pin-out is getting higher, and the pitch is getting finer. Thus, the conventional substrates, e.g., BT (bismaleimide triazine) cannot support these kinds of silicon chips anymore and a silicon interposer (substrate) is needed to redistribute the very fine-pitch and high pin-count pads on the chip to much larger pitch and less pin-count through the silicon vias on the silicon substrate. Depending on the via-size and pitch of the copper filled TSV, the effective CTE of the copper filled TSV interposer could be as high as $10x10^{-6}/degC.$ Consequently, the global thermal expansion mismatch between the silicon chip and the copper filled TSV substrate can be very large and the bumps (usually very small, e.g., microbumps) between them may not be able to survive under thermal conditions. In this study, the nonlinear stresses and strains in the microbumps between the silicon chip and copper filled TSV interposer (with and without underfills) have been determined for a wide-range of via sizes and pitches, and various temperature conditions. These results should be useful for (1) making a decision if underfills are necessary for the reliability of microbumps, and (2) selecting underfill materials to minimize the stresses and strains in the microbumps. |
| Starting Page | 1073 |
| Ending Page | 1081 |
| File Size | 1460704 |
| Page Count | 9 |
| File Format | |
| ISBN | 9781424422302 |
| ISSN | 05695503 |
| DOI | 10.1109/ECTC.2008.4550108 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-05-27 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Thermal stresses Capacitive sensors Copper Through-silicon vias Silicon Thermal expansion Dielectrics Temperature Tungsten Thermal loading |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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