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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Wei Lin Min Woo Lee |
| Copyright Year | 2008 |
| Description | Author affiliation: Amkor Technol., Chandler, AZ (Wei Lin; Min Woo Lee) |
| Abstract | The purpose of this paper was to evaluate the critical factors for package-on-package (PoP) and chip scale package (CSP) warpage control through experiments and modeling. Shadow moire was used to measure package warpage from room temperature to reflow temperature. The impact of new developments in laminate substrate technology including thin core and emerging low CTE core materials were emphasized in addition to the effects of die size and mold compound material. Warpage data for the package stackable flip chip CSP (PSfcCSP) used in high end PoP stacks as well as the newly developed thru-mold-via (TMV) technology were also reported. The evaluation showed the TMV technology had much less warpage than the conventional type of bare die PSfcCSP. A viscoelastic warpage model was developed to correlate the design of experiments (DOE) data. The viscoelastic property of four different mold compound materials was measured to obtain master curves and time temperature shifting functions by curve fitting the stress relaxation data. The correlation showed the results from the viscoelastic warpage models consistently agreed well with the test data in a wide range of design parameter space covered by the DOE. Furthermore, chemical shrinkage data was integrated with the viscoelastic relaxation to properly model the warpage during the mold curing step. The correlation data showed this was a much more effective approach to accurately model the actual shrinkage effect on warpage. |
| Starting Page | 1576 |
| Ending Page | 1581 |
| File Size | 917400 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424422302 |
| ISSN | 05695503 |
| DOI | 10.1109/ECTC.2008.4550186 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-05-27 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Viscosity Elasticity Chip scale packaging Temperature Semiconductor device modeling US Department of Energy Semiconductor device measurement Laminates Flip chip Stress measurement |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering |
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