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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Suarez, J.E. Johnson, B.E. El-Kareh, B. |
| Copyright Year | 1991 |
| Description | Author affiliation: IBM Corp., Essex Junction, VT, USA (Suarez, J.E.; Johnson, B.E.; El-Kareh, B.) |
| Abstract | The stability of polysilicon sheet resistance (R/sub s/) is studied as a function of conventional furnace anneal (CFA) and rapid thermal anneal (RTA). Polysilicon films of 100-nm, 200-nm, and 300-nm thickness are doped with boron, borofluoride, arsenic, or phosphorous, and subjected to a CFA anneal matrix simulating the thermal cycles of a digital-base BiCMOS process. RTA is introduced at the beginning or the end of the CFA anneal cycle to study its effectiveness in stabilizing the sheet resistance. CFA temperatures are varied from 550 degrees C to 900 degrees C, and RTA temperatures from 900 degrees C to 1100 degrees C. R/sub s/ is not only sensitive to anneal temperatures and duration, but also to the sequence in which the different thermal steps are introduced. A furnace anneal as low as 550 degrees C, following a furnace activation anneal of 900 degrees C or RTA at 1000 degrees C, results in a dramatic increase in R/sub s/. Then, subjecting the film to RTA at 1000 degrees C for five seconds recovers R/sub s/ to an extent which depends on dopant species and thermal history. The final thermal cycle in the sequence has the most dramatic effect on sheet resistance.< |
| Starting Page | 537 |
| Ending Page | 543 |
| File Size | 521388 |
| Page Count | 7 |
| File Format | |
| ISBN | 0780300122 |
| DOI | 10.1109/ECTC.1991.163929 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1991-05-11 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Thermal resistance Thermal stability Resistors Rapid thermal annealing Furnaces Temperature sensors Rapid thermal processing Boron Simulated annealing BiCMOS integrated circuits |
| Content Type | Text |
| Resource Type | Article |
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