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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Lei Ju Chakraborty, S. Roychoudhury, A. |
| Copyright Year | 2007 |
| Description | Author affiliation: Dept. of Comput. Sci., Nat. Univ. of Singapore (Lei Ju; Chakraborty, S.; Roychoudhury, A.) |
| Abstract | Recently there has been considerable interest in incorporating timing effects of micro architectural features of processors (e.g. caches and pipelines) into the schedulability analysis of tasks running on them. Following this line of work, in this paper the authors show how to account for the effects of cache-related preemption delay (CRPD) in the standard schedulability tests for dynamic priority schedulers like EDF. Even if the memory space of tasks is disjoint, their memory blocks usually map into a shared cache. As a result, task preemption may introduce additional cache misses which are encountered when the preempted task resumes execution; the delay due to these additional misses is called CRPD. Previous work on accounting for CRPD was restricted to only static priority schedulers and periodic task models. Our work extends these results to dynamic priority schedulers and more general task models (e.g. sporadic, generalized multiframe and recurring real-time). The authors show that the schedulability tests are useful through extensive experiments using synthetic task sets, as well as through a detailed case study |
| Starting Page | 1 |
| Ending Page | 6 |
| File Size | 230641 |
| Page Count | 6 |
| File Format | |
| ISBN | 9783981080124 |
| DOI | 10.1109/DATE.2007.364534 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-04-16 |
| Publisher Place | France |
| Access Restriction | Subscribed |
| Rights Holder | ESCI |
| Subject Keyword | Dynamic scheduling Testing Processor scheduling Delay effects Timing Vehicle dynamics Microarchitecture Pipelines Resumes Performance analysis |
| Content Type | Text |
| Resource Type | Article |
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