NDLI: Image Computation and Predicate Refinement for RTL Verilog using Word Level Proofs

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Challenges of Digital Consumer and Mobile SoC's: More Moore Possible?

Was Darwin Wrong? Has Design Evolution Stopped at the RTL Level... or Will Software and Custom Processors (or System-Level Design) Extend Moore's Law?

ATLAS: A Chip-Multiprocessor with Transactional Memory Support

A dynamically adaptive DSP for heterogeneous reconfigurable platforms

An 0.9 x 1.2", Low Power, Energy-Harvesting System with Custom Multi-Channel Communication Interface

An FPGA Based All-Digital Transmitter with Radio Frequency Output for Software Defined Radio

A Non-Intrusive Isolation Approach for Soft Cores

Unknown Blocking Scheme for Low Control Data Volume and High Observability

Test Cost Reduction for SoC Using a Combined Approach to Test Data Compression and Test Scheduling

High-Level Test Synthesis for Delay Fault Testability

Bus Access Optimisation for FlexRay-based Distributed Embedded Systems

A Decomposition-based Constraint Optimization Approach for Statically Scheduling Task Graphs with Communication Delays to Multiprocessors

Design Closure Driven Delay Relaxation Based on Convex Cost Network Flow

Simulation-based reusable posynomial models for MOS transistor parameters

Trade-Off Design of Analog Circuits using Goal Attainment and "Wave Front" Sequential Quadratic Programming

An Efficient Methodology for Hierarchical Synthesis of Mixed-Signal Systems with Fully Integrated Building Block Topology Selection

A Coefficient Optimization and Architecture Selection Tool for ΣΔ Modulators in MATLAB

Synthesis of Task and Message Activation Models in Real-Time Distributed Automotive Systems

An ILP Formulation for System-Level Application Mapping on Network Processor Architectures

A Smooth Refinement Flow for Co-designing HW and SW Threads

Speeding Up SystemC Simulation through Process Splitting

An FPGA Design Flow for Reconfigurable Network-Based Multi-Processor Systems on Chip

Hard Real-Time Reconfiguration Port Scheduling

An Efficient Algorithm for Online Management of 2D Area of Partially Reconfigurable FPGAs

Improving Utilization of Reconfigurable Resources Using Two Dimensional Compaction

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Efficient High-Performance ASIC Implementation of JPEG-LS Encoder

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Mapping Control-Intensive Video Kernels onto a Coarse-Grain Reconfigurable Architecture: the H.264/AVC Deblocking Filter

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SoC Testing Using LFSR Reseeding, and Scan-Slice- Based TAM Optimization and Test Scheduling

Optimized Integration of Test Compression and Sharing for SOC Testing

A Sophisticated Memory Test Engine for LCD Display Drivers

Formal Verification of a Pervasive Interconnect Bus System in a High-Performance Microprocessor

Low Cost Debug Architecture using Lossy Compression for Silicon Debug

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Design Space Exploration of Partially Re-configurable Embedded Processors

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Low Complexity LDPC Code Decoders for Next Generation Standards

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Pipelined Implementation of a Real Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell Architecture

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Remote Testing and Diagnosis of System-on-Chips Using Network Management Frameworks

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Mapping Multi-Dimensional Signals into Hierarchical Memory Organizations

The Impact of Loop Unrolling on Controller Delay in High Level Synthesis

Clock-Frequency Assignment for Multiple Clock Domain Systems-on-a-Chip

System-Level Process Variation Driven Throughput Analysis for Single and Multiple Voltage-Frequency Island Designs

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Automatic Synthesis of Compressor Trees: Reevaluating Large Counters

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Timing Simulation of Interconnected AUTOSAR Software-Components

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Diagnosis, Modeling and Tolerance of Scan Chain Hold-Time Violations

On Test Generation by Input Cube Avoidance

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Reversible Circuit Technology Mapping from Non-reversible Specifications

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Image Computation and Predicate Refinement for RTL Verilog using Word Level Proofs

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Joint Consideration of Fault-Tolerance, Energy-Efficiency and Performance in On-Chip Networks

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Image Computation and Predicate Refinement for RTL Verilog using Word Level Proofs

Content Provider	IEEE Xplore Digital Library
Author	Kroening, D. Sharygina, N.
Copyright Year	2007
Description	Author affiliation: ETH Zurich (Kroening, D.)
Abstract	Automated abstraction is the enabling technique for model checking large circuits. Predicate abstraction is one of the most promising abstraction techniques. It relies on the efficient computation of predicate images and the right choice of predicates. Existing algorithms use a net-list-level circuit model for computing predicate images. 1) This paper describes a proof-based algorithm that computes an over-approximation of the predicate image at the word-level, and thus, scales to larger circuits. 2) The previous work relies on the computation of the weakest preconditions in order to refine the set of predicates. In contrast to that, the paper proposed to extract predicates from a word-level proof to refine the set of predicates
Starting Page	1
Ending Page	6
File Size	155717
Page Count	6
File Format	PDF
ISBN	9783981080124
DOI	10.1109/DATE.2007.364481
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-04-16
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	ESCI
Subject Keyword	Hardware design languages Latches Concrete State-space methods Refining Logic circuits Circuit simulation Counting circuits Formal verification Explosions
Content Type	Text
Resource Type	Article

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