NDLI: Double-Via-Driven Standard Cell Library Design

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Challenges of Digital Consumer and Mobile SoC's: More Moore Possible?

Was Darwin Wrong? Has Design Evolution Stopped at the RTL Level... or Will Software and Custom Processors (or System-Level Design) Extend Moore's Law?

ATLAS: A Chip-Multiprocessor with Transactional Memory Support

A dynamically adaptive DSP for heterogeneous reconfigurable platforms

An 0.9 x 1.2", Low Power, Energy-Harvesting System with Custom Multi-Channel Communication Interface

An FPGA Based All-Digital Transmitter with Radio Frequency Output for Software Defined Radio

A Non-Intrusive Isolation Approach for Soft Cores

Unknown Blocking Scheme for Low Control Data Volume and High Observability

Test Cost Reduction for SoC Using a Combined Approach to Test Data Compression and Test Scheduling

High-Level Test Synthesis for Delay Fault Testability

Bus Access Optimisation for FlexRay-based Distributed Embedded Systems

A Decomposition-based Constraint Optimization Approach for Statically Scheduling Task Graphs with Communication Delays to Multiprocessors

Design Closure Driven Delay Relaxation Based on Convex Cost Network Flow

Simulation-based reusable posynomial models for MOS transistor parameters

Trade-Off Design of Analog Circuits using Goal Attainment and "Wave Front" Sequential Quadratic Programming

An Efficient Methodology for Hierarchical Synthesis of Mixed-Signal Systems with Fully Integrated Building Block Topology Selection

A Coefficient Optimization and Architecture Selection Tool for ΣΔ Modulators in MATLAB

Synthesis of Task and Message Activation Models in Real-Time Distributed Automotive Systems

An ILP Formulation for System-Level Application Mapping on Network Processor Architectures

A Smooth Refinement Flow for Co-designing HW and SW Threads

Speeding Up SystemC Simulation through Process Splitting

An FPGA Design Flow for Reconfigurable Network-Based Multi-Processor Systems on Chip

Hard Real-Time Reconfiguration Port Scheduling

An Efficient Algorithm for Online Management of 2D Area of Partially Reconfigurable FPGAs

Improving Utilization of Reconfigurable Resources Using Two Dimensional Compaction

Low-Power Warp Processor for Power Efficient High-Performance Embedded Systems

Using Dynamic Voltage Scaling to Reduce the Configuration Energy of Run Time Reconfigurable Devices

A Shift Register based Clause Evaluator for Reconfigurable SAT Solver

Efficient High-Performance ASIC Implementation of JPEG-LS Encoder

Improve CAM Power Efficiency Using Decoupled Match Line Scheme

Cyclostationary Feature Detection on a tiled-SoC

Mapping Control-Intensive Video Kernels onto a Coarse-Grain Reconfigurable Architecture: the H.264/AVC Deblocking Filter

An Efficient Hardware Architecture for H.264 Intra Prediction Algorithm

An FPGA Implementation of Decision Tree Classification

Radix 4 SRT Division with Quotient Prediction and Operand Scaling

SoC Testing Using LFSR Reseeding, and Scan-Slice- Based TAM Optimization and Test Scheduling

Optimized Integration of Test Compression and Sharing for SOC Testing

A Sophisticated Memory Test Engine for LCD Display Drivers

Formal Verification of a Pervasive Interconnect Bus System in a High-Performance Microprocessor

Low Cost Debug Architecture using Lossy Compression for Silicon Debug

An SoC Test Scheduling Algorithm using Reconfigurable Union Wrappers

Microprocessors in the Era of Terascale Integration

CMCal: An Accurate Analytical Approach for the Analysis of Process Variations with Non-Gaussian Parameters and Nonlinear Functions

A Symbolic Methodology for the Verification of Analog and Mixed Signal Designs

Efficient Nonlinear Distortion Analysis of RF Circuits

Nonlinearity Analysis of Analog/RF Circuits Using Combined Multisine and Volterra Analysis

Optimizing Analog Filter Designs for Minimum Nonlinear Distortions Using Multisine Excitations

Performance Analysis of Complex Systems by Integration of Dataflow Graphs and Compositional Performance Analysis

Tackling an Abstraction Gap: Co-simulating SystemC DE with Bluespec ESL

A Calculator for Pareto Points

Modeling and Simulation to the Design of ΣΔ Fractional-N Frequency Synthesizer

System Level Power Optimization of Sigma-Delta Modulator

Executable system-level specification models containing UML-based behavioral patterns

Assessing Carbon Nanotube Bundle Interconnect for Future FPGA Architectures

Two-Level Microprocessor-Accelerator Partitioning

Design Space Exploration of Partially Re-configurable Embedded Processors

Generating and Executing Multi-Exit Custom Instructions for an Adaptive Extensible Processor

Low Complexity LDPC Code Decoders for Next Generation Standards

Non-fractional parallelism in LDPC Decoder implementations

Minimum-Energy LDPC Decoder for Real-Time Mobile Application

Pipelined Implementation of a Real Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell Architecture

Implementation of AES/Rijndael on a dynamically reconfigurable architecture

Using the Inter- and Intra-Switch Regularity in NoC Switch Testing

Toward a Scalable Test Methodology for 2D-mesh Network-on-Chips

Remote Testing and Diagnosis of System-on-Chips Using Network Management Frameworks

Fast Memory Footprint Estimation based on Maximal Dependency Vector Calculation

Mapping Multi-Dimensional Signals into Hierarchical Memory Organizations

The Impact of Loop Unrolling on Controller Delay in High Level Synthesis

Clock-Frequency Assignment for Multiple Clock Domain Systems-on-a-Chip

System-Level Process Variation Driven Throughput Analysis for Single and Multiple Voltage-Frequency Island Designs

Reliability-Aware System Synthesis

Flexibility-oriented Design Methodology for Reconfigurable ΔΣ Modulators

Experimental Validation of a Tuning Algorithm for High-Speed Filters

Design of High-Resolution MOSFET-Only Pipelined ADCs with Digital Calibration

A New Technique for Characterization of Digital-to-Analog Converters in High-Speed Systems

Panel: "DFM/DFY: Should You Trust the Surgeon or the Family Doctor?"

Automatic Synthesis of Compressor Trees: Reevaluating Large Counters

Area Optimization of Multi-Cycle Operators in High-Level Synthesis

Data-Flow Transformations using Taylor Expansion Diagrams

Automatic Application Specific Floating-point Unit Generation

Time-Constrained Clustering for DSE of Clustered VLIW-ASP

Embedded Tutorial - Applications for Ubiquitous Computing and Communications

Timing Simulation of Interconnected AUTOSAR Software-Components

FPGA-based Networking Systems for High Data-rate and Reliable In-vehicle Communications

Low-g Accelerometer Fast Prototyping for Automotive Applications

Using an innovative SoC-level FMEA methodology to design in compliance with IEC61508

Using Partial-Run-Time Reconfigurable Hardware to accelerate Video Processing in Driver Assistance System

Towards a Methodology for the Quantitative Evaluation of Automotive Architectures

Dynamic Learning Based Scan Chain Diagnosis

Diagnosis, Modeling and Tolerance of Scan Chain Hold-Time Violations

On Test Generation by Input Cube Avoidance

Slow Write Driver Faults in 65nm SRAM Technology: Analysis and March Test Solution

On Power-profiling and Pattern Generation for Power-safe Scan Tests

Automatic Test Pattern Generation for Maximal Circuit Noise in Multiple Aggressor Crosstalk Faults

Temperature-aware NBTI modeling and the impact of input vector control on performance degradation

A Cross-Referencing-Based Droplet Manipulation Method for High-Throughput and Pin-Constrained Digital Microfluidic Arrays

Reversible Circuit Technology Mapping from Non-reversible Specifications

Distributed Power-Management Techniques for Wireless Network Video Systems

Improving the Fault Tolerance of Nanometric PLA Designs

Techniques for Designing Noise-Tolerant Multi-Level Combinational Circuits

An Efficient Code Compression Technique using Application-Aware Bitmask and Dictionary Selection Methods

Optimizing Instruction-set Extensible Processors under Data Bandwidth Constraints

Resource Prediction for Media Stream Decoding

Register Pointer Architecture for Efficient Embedded Processors

Feasibility of Combined Area and Performance Optimization for Superscalar Processors Using Random Search

A Decoupled Architecture of Processors with Scratch-Pad Memory Hierarchy

An Algorithm to Minimize Leakage through Simultaneous Input Vector Control and Circuit Modification

Understanding Voltage Variations in Chip Multiprocessors using a Distributed Power-Delivery Network

Process Variation Tolerant Low Power DCT Architecture

Statistical Dual-Vdd Assignment for FPGA Interconnect Power Reduction

Hardware Scheduling Support in SMP Architectures

A Scalable, Timing-Safe, Network-on-Chip Architecture with an Integrated Clock Distribution Method

Butterfly and Benes-Based on-Chip Communication Networks for Multiprocessor Turbo Decoding

Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms

Cost-Aware Capacity Optimization in Dynamic Multi-Hop WSNs

Design methods for Security and Trust

Emerging Solutions Technology and Business Views for the Ubiquitous Communication

Development of on Board, Highly Flexible, Galileo Signal Generator ASIC

New safety critical radio altimeter for Airbus and related design flow

Introducing New Verification Methods into a Company's Design Flow: An Industrial User's Point of View

Testable Design for Advanced Serial-Link Transceivers

Method for Reducing Jitter in Multi-Gigahertz ATE

Re-Configuration of Sub-blocks for Effective Application of Time Domain Tests

An ADC-BiST Scheme Using Sequential Code Analysis

Boosting SER Test for RF Transceivers by Simple DSP Technique

Novel Test Infrastructure and Methodology Used for Accelerated Bring-Up and In-System Characterization of the Multi-Gigahertz Interfaces on the Cell Processor

Evaluation of test measures for LNA production testing using a multinormal statistical model

Heterogeneous Systems on Chip and Systems in Package

Engineering Trust with Semantic Guardians

CATS: Cycle Accurate Transaction-driven Simulation with Multiple Processor Simulators

A One-Shot Configurable-Cache Tuner for Improved Energy and Performance

Design Fault Directed Test Generation for Microprocessor Validation

Impact of Description Language, Abstraction Layer, and Value Representation on Simulation Performance

Adaptive Power Management in Energy Harvesting Systems

Stochastic Modeling and Optimization for Robust Power Management in a Partially Observable System

Efficient and Scalable Compiler-Directed Energy Optimization for Realtime Applications

Peripheral-Conscious Scheduling on Energy Minimization for Weakly Hard Real-time Systems

Task Scheduling under Performance Constraints for Reducing the Energy Consumption of the GALS Multi-Processor SoC

Instruction Trace Compression for Rapid Instruction Cache Simulation

Efficient Code Density Through Look-up Table Compression

Microarchitectural Support for Program Code Integrity Monitoring in Application-specific Instruction Set Processors

Soft-core Processor Customization using the Design of Experiments Paradigm

Hot Topic II - Power Supply and Power Management in Ubicom

DATE 2007 "Best Industrial Designs" Session: From Algorithm to First 3.5G Call in Record Time - A Novel System Design Approach Based on Virtual Prototyping and its Consequences for Interdisciplinary System Design Teams

Portable Multimedia SoC Design: a Global Challenge

What If You Could Design Tomorrow's System Today?

Circuit-Level Modeling and Detection of Metallic Carbon Nanotube Defects in Carbon Nanotube FETs

Error Rate Reduction in DNA Self-Assembly by Non-Constant Monomer Concentrations and Profiling

Design and DfT of a High-Speed Area-Efficient Embedded Asynchronous FIFO

Test Quality Analysis and Improvement for an Embedded Asynchronous FIFO

Logic Level Fault Tolerance Approaches Targeting Nanoelectronics PLAs

A Multi-Core Debug Platform for NoC-Based Systems

Seamless Hardware/Software Performance Co-Monitoring in a Codesign Simulation Environment with RTOS Support

Incremental ABV for Functional Validation of TL-to-RTL Design Refinement

Efficient Testbench Code Synthesis for a Hardware Emulator System

Implementation of a Transaction Level Assertion Framework in SystemC

Automatic Generation of Functional Coverage Models from Behavioral Verilog Descriptions

Compositional Specification of Behavioral Semantics

Performance Analysis of Multimedia Applications using Correlated Streams

Simulation Platform for UHF RFID

Tool-support for the analysis of hybrid systems and models

Automatic Model Generation for Black Box Real-Time Systems

Panel Discussion: Life Begins at 65 - Unless You Are Mixed Signal?

Routing Table Minimization for Irregular Mesh NoCs

Congestion-Controlled Best-Effort Communication for Networks-on-Chip

Undisrupted Quality-of-Service during Reconfiguration of Multiple Applications in Networks on Chip

Testing in the Year 2020

Transaction Level Modelling of SCA Compliant Software Defined Radio Waveforms and Platforms PIM/PSM

Event Driven Data Processing Architecture

Reconfigurable System-on-Chip Data Processing Units for Space Imaging Instruments

Enabling certification for dynamic partial reconfiguration using a minimal flow

Identification of Process/Design Issues during 0.18μm Technology Qualification for Space Application

RECOPS: Reconfiguring Programmable Devices for Military Hardware Electronics

WAVSTAN: Waveform based Variational Static Timing Analysis

Rapid and Accurate Latch Characterization via Direct Newton Solution of Setup/Hold Times

Temperature and Voltage Aware Timing Analysis: Application to Voltage Drops

Accurate Timing Analysis using SAT and Pattern-Dependent Delay Models

CARAT: a Toolkit for Design and Performance Analysis of Component-Based Embedded Systems

Modeling and Simulation Alternatives for the Design of Networked Embedded Systems

Middleware Design Optimization of Wireless Protocols Based on the Exploitation of Dynamic Input Patterns

Leightweight Middleware for Seamless HW-SW Interoperability, with Application to Wireless Sensor Networks

A Middleware-centric Design Flow for Networked Embedded Systems

Dynamic Reconfiguration in Sensor Networks with Regenerative Energy Sources

Dynamic Power Management under Uncertain Information

Very Wide Register: An Asymmetric Register File Organization for Low Power Embedded Processors

Single-ended Coding Techniques for Off-chip Interconnects to Commodity Memory

PowerQuest: Trace Driven Data Mining for Power Optimization

System Level Assessment of an Optical NoC in an MPSoC Platform

Systematic Comparison between the Asynchronous and the Multi-Synchronous Implementations of a Network on Chip Architecture

Analytical Router Modeling for Networks-on-Chip Performance Analysis

Hard- and Software Modularity of the NOVA MPSoC Platform

Tutorial: The Methodological and Technological Dimensions of Technology Transfer for Embedded Systems in Aeronautics and Space

Energy Evaluation of Software Implementations of Block Ciphers under Memory Constraints

An Area Optimized Reconfigurable Encryptor for AES-Rijndael

Performance Aware Secure Code Partitioning

Energy and Execution Time Analysis of a Software-based Trusted Platform Module

Utilization of SECDED for Soft Error and Variation-Induced Defect Tolerance in Caches

Transient Fault Prediction Based on Anomalies in Processor Events

Low-Cost Protection for SER Upsets and Silicon Defects

Working with Process Variation Aware Caches

An Enhanced Technique for the Automatic Generation of Effective Diagnosis-oriented Test Programs for Processor

Functional and Timing Validation of Partially Bypassed Processor Pipelines

A Compositional Approach to the Combination of Combinational and Sequential Equivalence Checking of Circuits Without Known Reset States

Estimating Functional Coverage in Bounded Model Checking

Abstraction and Refinement Techniques in Automated Design Debugging

Automatic Hardware Synthesis from Specifications: A Case Study

pFFT in FastMaxwell: A Fast Impedance Extraction Solver for 3D Conductor Structures over Substrate

Optimization-based Wideband Basis Functions for Efficient Interconnect Extraction

Thermally Robust Clocking Schemes for 3D Integrated Circuits

Double-Via-Driven Standard Cell Library Design

Analysis of Power Consumption and BER of Flip-flop Based Interconnect Pipelining

A Future of Customizable Processors: Are We There Yet?

Fast and Accurate Routing Demand Estimation for Efficient Routability-driven Placement

Yield-aware Placement Optimization

Microarchitecture Floorplanning for Sub-threshold Leakage Reduction

Hot Topic 1: Industrial Applications

Flying Embedded: The Industrial Scene and Challenges for Embedded Systems in Aeronautics and Space

Compact Hardware Design of Whirlpool Hashing Core

An Efficient Polynomial Multiplier in GF(2m) and its Application to ECC Designs

Flexible Hardware Reduction for Elliptic Curve Cryptography in GF(2m)

Overcoming Glitches and Dissipation Timing Skews in Design of DPA-Resistant Cryptographic Hardware

Dynamic Critical Resistance: A Timing-Based Critical Resistance Model for Statistical Delay Testing of Nanometer ICs

Sensitivity Analysis for Fault-analysis and Tolerance in RF Front-end Circuitry

A Two-Tone Test Method for Continuous-Time Adaptive Equalizers

Worst-Case Design and Margin for Embedded SRAM

Pulse propagation for the detection of small delay defects

BIST Method for Die-Level Process Parameter Variation Monitoring in Analog/Mixed-Signal Integrated Circuits

A New Hybrid Solution to Boost SAT Solver Performance

QuteSAT: A Robust Circuit-based SAT Solver for Complex Circuit Structure

Boosting the Role of Inductive Invariants in Model Checking

Image Computation and Predicate Refinement for RTL Verilog using Word Level Proofs

Polynomial-Time Subgraph Enumeration for Automated Instruction Set Extension

Interrupt and Low-level Programming Support for Expanding the Application Domain of Statically-Scheduled Horizontal-Microcoded Architectures in Embedded Systems

DRIM : A Low Power Dynamically Reconfigurable Instruction Memory Hierarchy for Embedded Systems

SoftSIMD - Exploiting Subword Parallelism Using Source Code Transformations

A Process Splitting Transformation For Kahn Process Networks

Computing Synchronizer Failure Probabilities

Layout-Aware Gate Duplication and Buffer Insertion

Self Heating-Aware Optimal Wire Sizing under Elmore Delay Model

Statistical Blockade: A Novel Method for Very Fast Monte Carlo Simulation of Rare Circuit Events, and its Application

Clock Domain Crossing Fault Model and Coverage Metric for Validation of SoC Design

Fast Statistical Circuit Analysis with Finite-Point Based Transistor Model

Statistical simulation of high-frequency bipolar circuits

Hot Topic 2: Development and Industrialisation

Low Power Design on Algorithmic and Architectural Level: A Case Study of an HSDPA Baseband Digital Signal Processing System

Mapping the Physical Layer of Radio Standards to Multiprocessor Architectures

Development of an ASIP Enabling Flows in Ethernet Access Using a Retargetable Compilation Flow

An effective AMS Top-Down Methodology Applied to the Design of a Mixed-Signal UWB System-on-Chip

Behavioral Modeling of Delay-Locked Loops and its Application to Jitter Optimization in Ultra Wide-Band Impulse Radio Systems

Soft Error Rate Analysis for Sequential Circuits

Verification-Guided Soft Error Resilience

A Low-SER Efficient Core Processor Architecture for Future Technologies

Accurate and scalable reliability analysis of logic circuits

A New Asymmetric SRAM Cell to Reduce Soft Errors and Leakage Power in FPGA

Design Challenges at 65nm and Beyond

The ARTEMIS Cross-Domain Architecture for Embedded Systems

HW/SW Implementation from Abstract Architecture Models

Instruction-Set Customization for Real-Time Embedded Systems

A Novel Technique to Use Scratch-pad Memory for Stack Management

Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison

Task Scheduling for Reliable Cache Architectures of Multiprocessor Systems

Fast Positive-Real Balanced Truncation of Symmetric Systems Using Cross Riccati Equations

Random Sampling of Moment Graph: A Stochastic Krylov-Reduction Algorithm

Statistical Model Order Reduction for Interconnect Circuits Considering Spatial Correlations

A Sparse Grid based Spectral Stochastic Collocation Method for Variations-Aware Capacitance Extraction of Interconnects under Nanometer Process Technology

Simulation methodology and experimental verification for the analysis of substrate noise on LC-VCO's

Accurate Temperature-Dependent Integrated Circuit Leakage Power Estimation is Easy

Low-Overhead Circuit Synthesis for Temperature Adaptation Using Dynamic Voltage Scheduling

Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability

Efficient Computation of Discharge Current Upper Bounds for Clustered Sleep Transistor Sizing

Process Tolerant ß-ratio Modulation for Ultra-Dynamic Voltage Scaling

Panel Discussion: Towards Total Open Source in Aeronautics and Space?

A Tiny and Efficient Wireless Ad-hoc Protocol for Low-cost Sensor Networks

Scalable Reconfigurable Channel Decoder Architecture for Future Wireless Handsets

A New Pipelined Implementation for Minimum Norm Sorting used in Square Root Algorithm for MIMO-VBLAST Systems

Optimization of the "FOCUS" Inband-FEC Architecture for 10-Gbps SDH/SONET Optical Communication Channels

A Framework for System Reliability Analysis Considering Both System Error Tolerance and Component Test Quality

Experimental Evaluation of Protections Against Laser-induced Faults and Consequences on Fault Modeling

Evaluation of Design for Reliability Techniques in Embedded Flash Memories

Reduction of Detected Acceptable Faults for Yield Improvement via Error-Tolerance

Use of Statistical Timing Analysis on Real Designs

A Novel Criticality Computation Method in Statistical Timing Analysis

Efficient Computation of the Worst-Delay Corner

Accounting for Cache-Related Preemption Delay in Dynamic Priority Schedulability Analysis

Energy-Efficient Real-Time Task Scheduling with Task Rejection

Feasibility Intervals for Multiprocessor Fixed-Priority Scheduling of Arbitrary Deadline Periodic Systems

Energy Minimization with Soft Real-time and DVS for Uniprocessor and Multiprocessor Embedded Systems

Joint Consideration of Fault-Tolerance, Energy-Efficiency and Performance in On-Chip Networks

Impact of Process Variations on Multicore Performance Symmetry

Temperature Aware Task Scheduling in MPSoCs

Architectural Leakage-Aware Management of Partitioned Scratchpad Memories

Memory Bank Aware Dynamic Loop Scheduling

System Level Clock Tree Synthesis for Power Optimization

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Proceedings Design, Automation and Test in Europe

Double-Via-Driven Standard Cell Library Design

Content Provider	IEEE Xplore Digital Library
Author	Tsai-Ying Lin Tsung-Han Lin Hui-Hsiang Tung Rung-Bin Lin
Copyright Year	2007
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Yuan Ze Univ., Chung-Li (Tsai-Ying Lin)
Abstract	Double-via placement is important for increasing chip manufacturing yield. Commercial tools and recent work have done a great job for it. However, they are found with a limited capability of placing more double vias (called vial) between metal 1 and metal 2. Such a limitation is caused by the way we design the standard cells and can not be resolved by developing better tools. This paper presents a double-via-driven standard cell library design approach to solving this problem. Compared to the results obtained using a commercial cell library, our library on average achieves 78% reduction in dead vias and 95% reduction in dead vials at the expense of 11% increase in total via count. We achieve these results (almost) at no extra cost in total cell area and wire length
Starting Page	1
Ending Page	6
File Size	423244
Page Count	6
File Format	PDF
ISBN	9783981080124
DOI	10.1109/DATE.2007.364460
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-04-16
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	ESCI
Subject Keyword	Libraries Routing Wires Pins Costs Computer science Design engineering Computer aided manufacturing Standards development Bipartite graph
Content Type	Text
Resource Type	Article

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