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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Mueller, D. Graeb, H. Schlichtmann, U. |
| Copyright Year | 2007 |
| Description | Author affiliation: Inst. for Electron. Design Autom., TU Muenchen (Mueller, D.; Graeb, H.; Schlichtmann, U.) |
| Abstract | One of the main tasks in analog design is the sizing of the circuit parameters, such as transistor lengths and widths, in order to obtain optimal circuit performances, such as high gain or low power consumption. In most cases one performance can only be optimized at cost of others, therefore a sizing must aim at an optimal trade-off between the important circuit performances. This paper presents a new deterministic method to calculate the complete range of performance trade-offs, the so-called Pareto-optimal front, of a given circuit topology. Known deterministic methods solve a set of constrained multi-objective optimization problems independently of each other. The presented method minimizes a set of goal attainment (GA) optimization problems simultaneously. In a parallel algorithm, the individual GA optimization processes compare and exchange their iterative solutions. This leads to a significant improvement in the efficiency and quality of analog trade-off design |
| Starting Page | 1 |
| Ending Page | 6 |
| File Size | 216298 |
| Page Count | 6 |
| File Format | |
| ISBN | 9783981080124 |
| DOI | 10.1109/DATE.2007.364570 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-04-16 |
| Publisher Place | France |
| Access Restriction | Subscribed |
| Rights Holder | ESCI |
| Subject Keyword | Analog circuits Quadratic programming Electronic design automation and methodology Circuit topology Constraint optimization Optimization methods Performance gain Energy consumption Cost function Parallel algorithms |
| Content Type | Text |
| Resource Type | Article |
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