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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Sheibanyrad, A. Miro Panades, I. Greiner, A. |
| Copyright Year | 2007 |
| Description | Author affiliation: Pierre et Marie Curie Univ., Paris (Sheibanyrad, A.) |
| Abstract | This paper presents a systematic comparison between two different implementations of a distributed network on chip: fully asynchronous and multi-synchronous. The NoC architecture has been designed to be used in a globally asynchronous locally synchronous clusterized multi processors system on chip. The 5 relevant parameters are silicon area, network saturation threshold, communication throughput, packet latency and power consumption. Both architectures have been physically implemented and simulated by SystemC/VHDL co-simulation. The electrical parameters have also been evaluated by post layout SPICE simulation for a 90nm CMOS fabrication process, taking into account the long wire effects |
| Starting Page | 1 |
| Ending Page | 6 |
| File Size | 362101 |
| Page Count | 6 |
| File Format | |
| ISBN | 9783981080124 |
| DOI | 10.1109/DATE.2007.364439 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-04-16 |
| Publisher Place | France |
| Access Restriction | Subscribed |
| Rights Holder | ESCI |
| Subject Keyword | Network-on-a-chip System-on-a-chip Silicon Throughput Delay Energy consumption SPICE CMOS process Fabrication Wire |
| Content Type | Text |
| Resource Type | Article |
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