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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Dittmann, F. Frank, S. |
| Copyright Year | 2007 |
| Description | Author affiliation: Heinz Nixdorf Inst., Paderborn Univ. (Dittmann, F.; Frank, S.) |
| Abstract | When modern partially and dynamically reconfigurable FPGAs are to be used as resources in hard real-time systems, the two dimensions area and time have to be considered in the focus of availability and deadlines. In particular, area requirements must be guaranteed for the tasks' duration. While execution environments that abstract the space demand of tasks exist and methods for occupancy of resources over time are discussed in the literature, few works focus on another fundamental bottleneck, the reconfiguration port. As all resource requests are served by this mutually exclusive device, profound concepts for scheduling the port access are vital requirements for FPGA realtime scheduling. Nevertheless, as the port must be accessed sequentially, we can inherit and apply monoprocessor scheduling concepts that are well researched. In this paper, we introduce monoprocessor scheduling algorithms for the reconfiguration port of FPGAs |
| Starting Page | 1 |
| Ending Page | 6 |
| File Size | 571015 |
| Page Count | 6 |
| File Format | |
| ISBN | 9783981080124 |
| DOI | 10.1109/DATE.2007.364578 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-04-16 |
| Publisher Place | France |
| Access Restriction | Subscribed |
| Rights Holder | ESCI |
| Subject Keyword | Field programmable gate arrays Real time systems Scheduling algorithm Operating systems Processor scheduling Embedded system Parallel machines Dynamic scheduling Availability Table lookup |
| Content Type | Text |
| Resource Type | Article |
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