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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Rhod, E.L. Lisboa, C.A. Carro, L. |
| Copyright Year | 2007 |
| Description | Author affiliation: Inst. de Informatica, Univ. Fed. do Rio Grande do Sul, Porto Alegre (Rhod, E.L.; Lisboa, C.A.; Carro, L.) |
| Abstract | Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions have started to be investigated by the community, the full use of future resources in circuits tolerant to SETs, without performance, area or power penalties, is still an open research issue. This paper introduces MemProc, an embedded core processor with extra low SER sensitivity, and with no performance or area penalty when compared to its RISC counterpart. Central to the SER reduction are the use of new magnetic memories (MRAM and FRAM) and the minimization of the combinational logic area in the core. This paper shows the results of fault injection in the MemProc core processor and in a RISC machine, and compares performance and area of both approaches. Experimental results show a 29 times increase in fault tolerance, with up to 3.75 times in performance gains and 14 times less sensible area |
| Starting Page | 1 |
| Ending Page | 6 |
| File Size | 249305 |
| Page Count | 6 |
| File Format | |
| ISBN | 9783981080124 |
| DOI | 10.1109/DATE.2007.364502 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-04-16 |
| Publisher Place | France |
| Access Restriction | Subscribed |
| Rights Holder | ESCI |
| Subject Keyword | Magnetic cores Reduced instruction set computing Error analysis Logic devices Combinational circuits Sequential circuits Magnetic memory Random access memory Ferroelectric films Nonvolatile memory |
| Content Type | Text |
| Resource Type | Article |
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